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12 - bit, 2.0 gsps, 1.3 v/2.5 v analog - to - digital converter data sheet ad9625 features 12 - bit 2.0 gsps adc, no missing codes sfdr = 80 dbc, ain up to 1 ghz at ?1 dbfs, 2.0 gsps sfdr = 7 6 dbc, ain up to 1.8 ghz at ?1 dbfs, 2.0 gsps snr = 59 dbfs, ain up to 1 ghz at ?1 dbfs, 2.0 gsps snr = 5 8 dbfs, ain up to 1.8 ghz at ?1 dbfs, 2.0 gsps noise f loor = ? 1 49 .5 dbfs/hz at 2.0 gsps power consumption: 3.5 w at 2.0 gsps differential analog input : 1.1 v p - p differential clock input high speed 6 - or 8 - lane jesd 204b serial output sub c lass 1: 5.0 gbps at 2. 0 gsps two independent decimate by 8 or decimate by 16 filters with 10 - bit ncos supply voltages: 1.3 v, 2.5 v serial port control flexible digital output modes built - in selectable digital test patterns applications spectrum analyzers military communications r adar high performance digital storage oscilloscopes active jamming/antijamming electronic surveillance and countermeasures functional block dia gram figure 1. general description the ad9625 is a 12 - bit monolithic sampling analog - to - digital converter (adc) that operates at conversion rates of up to 2.0 giga samples per second (gsps). this product is designed for sampling wide bandwidth analog signals up to the second nyquist zone. the combina tion of wide input bandwidth, high sampling rate, and excellent linearity of the ad9625 is ideally suited for spectrum analyzers, data acquisition systems, and a wide assortment of military electr onics applications, such as radar and jamming/antijamming measures. the analog input, clock, and sysref signals are differential inputs. the jesd204b - based high speed serialized output is configurable in a variety of one - , two - , four - , six - , or eight - lane configurations. the product is specified over the industrial temperature range of ? 40 c to +85 c . product highlights 1. high p erformance : e xceptional sfdr i n high sample rate applications, d irect rf s ampling , and on - chip reference. 2. f lexible digital data out put formats based on the jesd204b specification . 3. c ontrol path spi interface port that supports various product features and functions, such as data formatting, gain , and offset calibration values. 11814-001 avdd agnd drvdd drgnd cmos digital input/output ddc f s /8 or f s /16 digital interface and control control registers vin+ vin? vcm sysref clk rbias adc core reference clock management sdio sclk csb fd serdout[0] serdout[1] serdout[2] serdout[3] serdout[4] serdout[5] serdout[6] serdout[7] syncinb divclk rstb irq ad9625 jesd204b interface cmos digital input/ output lvds digital input/ output rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result fr om its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one tec hnology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2014 analog devices, inc. all rights reserved. technical support www.analog.com
ad9625 data sheet rev. 0 | page 2 of 56 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? dc specifications ......................................................................... 3 ? ac specifications .......................................................................... 4 ? digital specifications ................................................................... 4 ? switching specifications .............................................................. 6 ? timing specifications .................................................................. 6 ? absolute maximum ratings ....................................................... 8 ? thermal characteristics .............................................................. 8 ? esd caution .................................................................................. 8 ? pin configuration and function descriptions ............................. 9 ? typical performance characteristics ........................................... 15 ? equivalent test circuits ................................................................. 18 ? theory of operation ...................................................................... 19 ? adc architecture ...................................................................... 19 ? fast detect ................................................................................... 19 ? gain threshold operation ........................................................ 19 ? test modes ................................................................................... 20 ? digital downconverters (ddc) ................................................... 21 ? frequency synthesizer and mixer ............................................ 21 ? high bandwidth decimator ...................................................... 21 ? low bandwidth decimator ....................................................... 22 ? analog input considerations ........................................................ 23 ? clock input considerations ...................................................... 23 ? dc coupling ............................................................................... 23 ? calibration ................................................................................... 23 ? digital outputs ............................................................................... 24 ? introduction to jesd204b interface ........................................ 24 ? functional overview ................................................................. 24 ? jesd204b link establishment ................................................. 25 ? physical layer output ................................................................ 29 ? scrambler ..................................................................................... 29 ? tail bits ........................................................................................ 29 ? ddc modes (single and dual) ................................................ 29 ? checksum ................................................................................... 30 ? 8-bit/10-bit encoder control ................................................... 30 ? initial lane alignment sequence (ilas) ................................ 30 ? lane synchronization ................................................................ 30 ? jesd204b application layers .................................................. 31 ? frame alignment character insertion .................................... 33 ? thermal considerations ............................................................ 33 ? power supply considerations ................................................... 33 ? serial port interface (spi) .............................................................. 35 ? configuration using the spi ..................................................... 35 ? hardware interface ..................................................................... 35 ? memory map .................................................................................. 36 ? reading the memory map register ......................................... 36 ? memory map registers ............................................................. 36 ? outline dimensions ....................................................................... 54 ? ordering guide .......................................................................... 54 ? revision history 5/14revision 0: initial version
data sheet ad9625 specifications dc specifications avdd1 = dvdd1 = drvdd1 = 1.3 v, avdd2 = dvdd2 = drvdd2 = 2.5 v, specified maximum sampling rate, 1.2 v internal reference, ain = ?1.0 dbfs, default spi setti ngs, dc - coupled output data, unless o therwise noted. table 1 . parameter test conditions/comments temperature 1 min typ max unit speed grade 2.0 gsps resolution 12 bits accuracy no missing codes full guaranteed offset error full 0.5 lsb gain error full 8 %fsr differential nonlinearity (dnl) full 0.3 0.3 lsb integral nonlinearity (inl) full 0.9 3.6 lsb analog inputs differential input voltage range internal v ref = 1.2 v full 1.1 v p -p resistance 25c 100 capacitance 25c 1.5 pf internal common - mode voltage (v cm ) full 493 525 564 mv analog full power bandwidth 100 differential termination 25c 2.0 ghz input referred noise 25c 3.5 lsb rms power supplies avdd1 full 1.26 1.3 1.32 v avdd2 full 2.4 2.5 2.6 v drvdd1 full 1.26 1.3 1.32 v drvdd2 full 2.4 2.5 2.6 v dvdd1 full 1.26 1.3 1.32 v dvdd2 full 2.4 2.5 2.6 v dvddio full 2.4 2.5 2.6 v spi_vddio full 2.4 2.5 2.6 v i avdd1 full 1120 1222 ma i avdd2 full 383 460 ma i drvdd1 full 456 490 ma i drvdd2 full 9 10 ma i dvdd1 full 430 410 ma i dvdd2 full <1 ma i dvddio full <1 ma i spi_vddio full <1 ma power dissipation full 3.48 3.80 w 1 full temperature range is ?40c to +85c measured at the case (t c ). rev. 0 | page 3 of 56
ad9625 data sheet ac specifications a vdd1 = dvdd1 = drvdd1 = 1.3 v, avdd2 = dvdd2 = drvdd2 = 2.5 v, specified maximum sampling, 1.2 v internal reference, ain = ?1.0 dbfs, sample clock input = 1.65 v p - p differential, default spi settings, unless otherwise no ted. table 2 . parameter test conditions/comments temperature min typ max unit speed grade 2.0 gsps analog input full scale full 1.1 v p -p noise density 25c ? 149.5 dbfs/hz signal -to - noise ratio (snr) f in = 100 mhz 25c 59.5 dbfs f in = 500 mhz 25c 59.4 dbfs f in = 1000 mhz 25c 59.0 dbfs f in = 1800 mhz full 55.4 58.2 dbfs signal -to - noise and distortion (sinad) f in = 100 mhz 25c 58.4 dbc f in = 500 mhz 25c 58.4 dbc f in = 1000 mhz 25c 58.0 dbc f in = 1800 mhz full 54.1 57.2 dbc effective number of bits (enob) f in = 100 mhz 25c 9.4 bits f in = 500 mhz 25c 9.4 bits f in = 1000 mhz 25c 9.3 bits f in = 1800 mhz full 8.7 9.2 bits spurious free dynamic range (sfdr) including second or third harmonic f in = 100 mhz 25c 80 dbc f in = 500 mhz 25c 81 dbc f in = 1000 mhz 25c 80 dbc f in = 1800 mhz full 67 76 dbc worst other spur excluding second or third harmonic f in = 100 mhz 25c 80 dbc f in = 500 mhz 25c 86 dbc f in = 1000 mhz 25c 83 dbc f in = 1800 mhz full 73 85 dbc two - tone intermodulation distortion (imd) at ?7 dbfs per tone f in1 = 728.5 mhz, f in2 = 731.5 mhz 25c 82.8 dbc f in1 = 1805.5 mhz, f in2 = 1808.5 mhz 25c 77.6 dbc digital specificatio ns avdd1 = dvdd1 = drvdd1 = 1.3 v, avdd2 = dvdd2 = drvdd2 = 2.5 v, specified maximum sampling rate, 1.2 v internal reference, ain = ? 1.0 dbfs, default spi settings, unless otherwise noted. table 3 . parameter temperature min typ max unit clock inputs (clk+, clk?) differential input voltage full 250 1800 mv p -p common - mode input voltage full 0.88 v input resistance (differential) full 57 k input capacitance full 1.5 pf sysref inputs (sysref+, sysref ? ) differential input voltage full 250 1800 mv p -p common - mode input voltage full 0.88 v rev. 0 | page 4 of 56
data sheet ad9625 parameter temperature min typ max unit input resistance (differential) full 100 input capacitance full 1.5 pf logic inputs (sdio, sclk, csb) logic compliance cmos voltage logic 1 full 0.8 spi_dvddio v logic 0 full 0.5 v input resistance full 30 k input capacitance full 0.5 pf syncb+ / syncb? in put (syncinb+, syncinb?) logic compliance full lvds input voltage differential full 250 1200 mv p -p common mode full 1.2 v input resistance (differential) full 20 k input capacitance full 2.5 pf logic output (sdio) logic compliance cmos voltage logic 1 (i oh = 800 a) full 0.8 spi_vddio v logic 0 (i ol = 50 a) full 0.3 v digital outputs (serdout [ x ] ) compliance full cml output voltage differential full 360 700 800 mv p -p offset full drvdd/2 mv p -p differential return loss (rl diff ) 1 25c 8 db common - mode return loss (rl cm ) 1 25c 6 db differential termination impedance full 100 reset ( rstb ) voltage logic 1 full 0.8 dvddio v logic 0 full 0.5 v input resistance (differential) full 20 k input capacitance full 2.5 pf fast detect (fd) and interrupt (irq) logic compliance cmos voltage logic 1 full 0.8 dvddio v logic 0 full 0.5 v input resistance (differential) full 20 k input capacitance full 2.5 pf 1 differential and common - mode return loss measured from 100 mhz to 0.75 baud rate. rev. 0 | page 5 of 56
ad9625 data sheet switching s pecifications avdd1 = dvdd1 = drvdd1 = 1.3 v, avdd2 = dvdd2 = drvdd2 = 2.5 v, specified maximum sampling rate, 1.2 v internal reference, ain = ?1.0 dbfs, default spi settings, unless otherwise noted. table 4 . parameter test conditions/comments temperature min typ max unit clock (clk ) maximum clock rate full 2000 msps minimum clock rate full 330 1 msps clock pulse width high full 50 5 % duty cycle clock pulse width low full 50 5 % duty cycle sysref (sysref ) 2 setup time (t s u_ sr ) 25c +200 ps hold time (t h_ sr ) 25c ? 100 ps fast detect output (fd) latency full 82 clock c ycles output parameters ( serdout[x] ) rise time 25c 70 ps fall time 25c 70 ps pipeline latency generic 8 - lane mo de 25c 226 clock cycles aperture delay full 180 ps uncertainty (jitter) full 55 f s rms out -of -r ange recovery time full 2 clock cycles 1 must use a two - lane, generic output lane configuration for minimum sample rate. for more information, s ee the lane table in the jesd204b specification document. 2 sysref setup and hold times are defined with respect to the rising sysref edge and rising clock edge. positive setup time leads the clock edge. negative hold time also leads the clock edge. timing specification s table 5 . parameter test conditions/comments min typ max unit spi timing requirements t ds setup time between the data and the rising edge of sclk 2 ns t dh hold time between the data and the rising edge of sclk 2 ns t clk period of the sclk 40 ns t s setup time between csb and sclk 2 ns t h hold time between csb and sclk 2 ns t high minimum period that sclk should be in a logic high state 10 ns t low minimum period that sclk should be in a logic low state 10 ns t en_sdio time required for the sdio pin to switch from an input to an output relative to the sclk falling edge (not shown in figure 3 ) 10 ns t dis_sdio time required for the sdio pin to switch from an output to an input relative to the sclk rising edge (not shown in figure 3 ) 10 ns rev. 0 | page 6 of 56
data sheet ad9625 timing diagram s figure 2. sysref setup and hold timing figure 3 . serial port interface timing diagram (msb first) figure 4 . clk input and dout timing relationship (generic eight - lane mode) 11814-202 clk+ clk? sysref+ sysref? t su_sr t h_sr 11814-203 don?t care don?t care don?t care don?t care sdio sclk csb t s t ds t dh t high t low t clk t h r/w a14 a13 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 a b c d e f g h i j a b c d e f g h i j f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j a b c d e f g h i j f g h i j a b c d e f g h i j a b c d e f g h i j jesd204b interface m = 1; l = 8; n = 12; n' = 16; cf = 0; cs = 0; cs = 0...4; k = 32; hd = 1; f = 1 500ps min (2.0ghz) clk+ (encode clock) lane a @ 5.0gbps lane b @ 5.0gbps lane c @ 5.0gbps lane d @ 5.0gbps lane e @ 5.0gbps lane f @ 5.0gbps lane g @ 5.0gbps lane h @ 5.0gbps sample n + 3 [3:0], cccc sample n + 7 [3:0], cccc sample n + 11 [3:0], cccc sample n + 15 [3:0], cccc sample n + 2 [3:0], cccc sample n + 6 [3:0], cccc sample n + 10 [3:0], cccc sample n + 14 [3:0], cccc sample n + 1 [3:0], cccc sample n + 5 [3:0], cccc sample n + 9 [3:0], cccc sample n + 13 [3:0], cccc sample n [3:0], cccc sample n + 4 [3:0], cccc sample n + 8 [3:0], cccc sample n + 12 [3:0], cccc sample n + 3 [11:4] sample n + 7 [11:4] sample n + 11 [11:4] sample n + 15 [11:4] sample n + 2 [11:4] sample n + 6 [11:4] sample n + 10 [11:4] sample n + 14 [11:4] sample n + 1 [11:4] sample n + 5 [11:4] sample n + 9 [11:4] sample n + 13 [11:4] sample n [11:4] sample n + 4 [11:4] sample n + 8 [11:4] sample n + 12 [11:4] f = 1 octets f = 1 octets f = 1 octets f = 1 octets 11814-003 rev. 0 | page 7 of 56
ad9625 data sheet absolute maximum rat ings table 6 . parameter rating electrical avdd1to agnd ? 0.3 v to +1.32 v avdd2 to agnd ? 0.3 v to +2.75 v drvdd1 to drgnd ? 0.3 v to +1.32 v drvdd2 to drgnd ? 0.3 v to +2.75 v dvdd1 to dgnd ? 0.3 v to +1.32 v dvdd2 to dgnd ? 0.3 v to + 2.75 v dvddio to dgnd ? 0.3 v to +3.63 v spi_vddio to dgnd ? 0.3 v to +3.63 v agnd to drgnd ? 0.3 v to +0.3 v vin to agnd ? 0.3 v to avdd1+ 0.2 v vcm to agnd ? 0.3 v to avdd1+ 0.2 v vmon to agnd ? 0.3 v to avdd1+ 0.2 v clk to agnd ? 0.3 v to avdd1+ 0.2 v sysref to agnd ? 0.3 v to avdd1+ 0.2 v syncinb to drgnd ? 0.3 v to drvdd2 + 0.2 v sclk to drgnd ? 0.3 v to spi_vddio + 0.2 v sdio to drgnd ? 0.3 v to spi_vddio + 0.2 v irq to drgnd ? 0.3 v to dvddio + 0.2 v rstb to drgnd ? 0.3 v to dvddio + 0.2 v csb to drgnd ? 0.3 v to spi_vddio + 0.2 v fd to drgnd ? 0.3 v to dvddio + 0.2 v divclk to drgnd ? 0.3 v to drvdd2 + 0.2 v serdout[x] to drgnd ? 0.3 v to drvdd1 + 0.2 v environmental operating temperature range ? 40c to +85c maximum junction temperature 90c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal characteristics the following characteristics are for a 4 - layer and 10 - layer printed circuit board (pcb). table 7 . thermal resistance pcb t a (c) ja (c/w) jt (c/w) jb (c/w) jc (c/w) 4 - layer 85.0 18.7 0.61 6.1 1.4 10- layer 85.0 11.5 0.61 4.1 n/a 1 1 n/a means not applicable. esd caution rev. 0 | page 8 of 56
data sheet ad9625 pin con figuration and function descrip tions figure 5 . pin configuratio n avdd2 avdd1 dvdd2 dvdd1 drvdd2 drvdd1 dvddio spi_vd dio agnd dgnd drgnd dnc or bypass with cap agnd agnd agnd dvdd1 dgnd dvdd1 dgnd dvdd1 dgnd dvdd1 dgnd drgnd drvdd1 drvdd1 a b c d e f g h j k l m n p dnc agnd agnd agnd dvdd1 dgnd dvdd1 dgnd dvdd1 dgnd dvdd1 drgnd serdout [7]+ serdout [7]? agnd agnd agnd dvdd1 dgnd dvdd1 dgnd dvdd1 dgnd rstb syncinb? drgnd serdout [6]+ serdout [6]? avdd1 agnd agnd dnc dvdd2 spi_vddio csb sclk sdio dnc syncinb+ drgnd serdout [5]+ serdout [5]? agnd avdd1 agnd agnd vmon dvddio dvddio irq fd agnd dgnd drgnd serdout [4]+ serdout [4]? avdd2 agnd avdd1 agnd agnd agnd agnd agnd rbias_ext agnd dgnd drgnd drvdd1 drvdd1 vcm avdd2 agnd avdd1 avdd1 avdd1 avdd1 avdd1 avdd1 agnd dgnd drgnd serdout [3]+ serdout [3]? agnd agnd avdd2 avdd2 avdd2 avdd2 avdd2 avdd2 avdd2 agnd dgnd drgnd serdout [2]+ serdout [2]? vin+ agnd agnd agnd agnd agnd agnd agnd agnd agnd dgnd drgnd serdout [1]+ serdout [1]? vin? agnd agnd agnd agnd agnd agnd agnd agnd agnd dnc drgnd serdout [0]+ serdout [0]? agnd agnd avdd2 avdd2 avdd2 avdd2 avdd2 avdd2 avdd2 agnd dnc drvdd1 drvdd1 drvdd1 vm_byp avdd2 agnd avdd1 avdd1 avdd1 avdd1 avdd1 avdd1 agnd dnc rext vp_byp drgnd avdd2 agnd agnd avdd1 agnd agnd agnd agnd agnd agnd agnd drgnd drvdd2 divclk? avdd2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 agnd avdd1 avdd1 agnd clk+ clk? agnd sysref+ sysref? agnd drgnd drvdd2 divclk+ ad9625 top view (not to scale) 11814-009 notes 1. dnc = do not connect. do not connect to this pin. leave this pin floating. rev. 0 | page 9 of 56
ad9625 data sheet table 8 . pin function descriptions (by pin number) pin no. mnemonic type description a1 to a3 agnd ground adc analog ground . these pins connect to the analog ground plane. a4 avdd1 power adc analog power supply (1.30 v). a5 agnd ground adc analog ground . this pin connects to the analog ground plane. a6 avdd2 power adc analog power supply (2.50 v) . a7 vcm output analog input, common mode (0.525 v). a8 agnd ground adc analog ground . this pin connects to the analog ground plane. a9 vin+ input differential analog input , true . a10 vin? input differential analog input, complement . a11 agnd ground adc analog ground. this pin connects to the analog ground plane. a12 vm_byp input voltage bypass. a13 avdd2 power adc analog power supply (2.50 v) . a14 avdd2 power adc analog power supply (2.50 v) . b1 to b4 agnd ground adc analog ground . these pins connect to the analog ground plane. b5 avdd1 power adc analog power supply (1.30 v) . b6 agnd ground adc analog ground . this pin connects to the analog ground plane. b7 avdd2 power adc analog power supply (2.50 v) . b8 to b11 agnd ground adc analog ground . these pins connect to the analog ground plane. b12 avdd2 power adc analog power supply (2.50 v) . b13, b14 agnd ground adc analog ground . these pins connect to the analog ground plane. c1 to c5 agnd ground adc analog ground . these pins connect to the analog ground plane. c6 avdd1 power adc analog power supply (1.30 v) . c7 agnd ground adc analog ground . this pin connects to the analog ground plane. c8 avdd2 power adc analog power supply (2.50 v) . c9, c10 agnd ground adc analog ground . these pins connect to the analog ground plane. c11 avdd2 power adc analog power supply (2.50 v) . c12, c13 agnd ground adc analog ground . these pins connect to the analog ground plane. c14 avdd1 power adc analog power supply ( 1.30 v) . d1 to d3 dvdd1 power adc digital power supply (1.30 v). d4 dnc n/a do not connect. do not connect to this p in. leave this pin floating . d5, d6 agnd ground adc analog ground . these pins connect to the analog ground plane. d7 avdd1 power adc analog power supply ( 1.30 v) . d8 avdd2 power adc analog power supply (2.50 v) . d9, d10 agnd ground adc analog ground . these pins connect to the analog ground plane. d11 avdd2 power adc analog power supply (2.50 v) . d12 to d14 avdd1 power adc analog power supply ( 1.30 v) . e1 to e3 dgnd ground digital control ground supply. these pins connect to the digital ground plane. e4 dvdd2 power adc digital power supply (2.5 v). e5 vmon output ctat voltage monitor output. e6 agnd ground adc analog ground . this pin connects to the analog ground plane. e7 avdd1 power adc analog power supply ( 1.30 v) . e8 avdd2 power adc analog power supply (2.50 v) . e9, e10 agnd ground adc analog ground . these pins connect to the analog ground plane. e11 avdd2 power adc analog power supply (2.50 v) . e12 avdd1 power adc analog power supply ( 1.30 v) . e13, e14 agnd ground adc analog ground . these pins connect to the analog ground plane. f1 to f3 dvdd1 power adc digital power supply (1.30 v). f4 spi_vddio power spi digital power supply (2.50 v). f5 dvddio power digital i/o power supply (2.50 v). f6 agnd ground adc analog ground . this pin connects to the analog ground plane. f7 avdd1 power adc analog power supply ( 1.30 v) . f8 avdd2 power adc analog power supply (2.50 v) . f9, f10 agnd ground adc analog ground . these pins connect to the analog ground plane. rev. 0 | page 10 of 56
data sheet ad9625 pin no. mnemonic type description f11 avdd2 power adc analog power supply (2.50 v) . f12 avdd1 power adc analog power supply ( 1.30 v) . f13 agnd ground adc analog ground . this pin connects to the analog ground plane. f14 clk+ input adc clock input, true. g1 to g3 dgnd ground digital control ground supply. these pins connect to the digital ground plane. g4 csb input spi chip select cmos input. active low. g5 dvddio power digital i/o power s upply (2.50 v). g6 agnd ground adc analog ground . this pin connects to the analog ground plane. g7 avdd1 power adc analog power supply ( 1.30 v) . g8 avdd2 power adc analog power supply (2.50 v) . g9, g10 agnd ground adc analog ground . these pins connect to the analog ground plane. g11 avdd2 power adc analog power supply (2.50 v) . g12 avdd1 power adc analog power supply ( 1.30 v) . g13 agnd ground adc analog ground . this pin connects to the analog ground plane. g14 clk? input adc clock input, complement. h1 to h3 dvdd1 power adc digital power supply (1.30 v). h4 sclk input spi serial clock cmos input. h5 irq output interrupt request output signal. h6 agnd ground adc analog ground . this pin connects to the analog ground plane. h7 avdd1 power adc analog power supply ( 1.30 v) . h8 avdd2 power adc analog power supply (2.50 v) . h9, h10 agnd ground adc analog ground . these pins connect to the analog ground plane. h11 avdd2 power adc analog power supply (2.50 v) . h12 avdd1 power adc analog power supply ( 1.30 v) . h13, h14 agnd ground adc analog ground . these pins connect to the analog ground plane. j1 to j3 dgnd ground digital control ground supply. these pins connect to the digital ground plane. j4 sdio i/o spi serial data cmos input/output; scan output 1. j5 fd output fast detect output. this pin requires an external 10 k resistor connected to ground. j6 rbias_ext input reference bias. this pin requires an external 10 k resistor connected to ground. j7 avdd1 power adc analog power supply ( 1.30 v) . j8 avdd2 power adc analog power supply (2.50 v) . j9, j10 agnd ground adc analog ground . these pins connect to the analog ground plane. j11 avdd2 power adc analog power supply (2.50 v) . j12 avdd1 power adc analog power supply ( 1.30 v) . j13 agnd ground adc analog ground . this pin connects to the analog ground plane. j14 sysref+ input system reference chip synchronization, true. k1 to k2 dvdd1 power adc digital power supply (1.30 v). k3 rstb input chip digital reset, active low. k4 dnc n/a do no t connect . do not connect to this pin. leave this pin floating . k5 to k13 agnd ground adc analog ground . these pins connect to the analog ground plane. k14 sysref? input system reference chip synchronization, complement. l1 dgnd ground digital control ground supply. th is pin connect s to the digital ground plane. l2 dnc n/a do no t connect. do not connect to this pin . leave this pin floating . l3 syncinb? input synchronization, complement. l4 syncinb+ input synchronization, true. syncinb lvds input (active low, true). l5 to l 9 dgnd ground digital control ground supply. these pins connect to the digital ground plane. l10 to l12 dnc n/a do not connect. do not connect to these pins. leave th ese pin s floating . l13, l14 agnd ground adc analog ground . these pins connect to the analog ground plane. m1 to m10 drgnd ground digital driver ground supply. these pins connect to the digital driver ground plane. m11 drvdd1 power power supply (1.3 v) reference clock divider, vco, and synthesizer. m12 rext input external resistor, 10 k to ground. m13, m14 drgnd ground digital driver ground supply. this pin connects to the digital driver ground plane. rev. 0 | page 11 of 56
ad9625 data sheet pin no. mnemonic type description n1 drvdd1 power serial digital power supply (1.3 v). n2 serdout [ 7 ] + output lane 7 cml output data, true. n3 serdout [ 6 ] + output lane 6 cml output data, true. n4 serdout [ 5 ] + output lane 5 cml output data, true. n5 serdout [ 4 ] + output lane 4 cml output data, true. n6 drvdd1 power serial digital power supply (1.3 v). n7 serdout [ 3 ] + output lane 3 cml output data, true. n8 serdout [ 2 ] + output lane 2 cml output data, true. n9 serdout [ 1 ] + output lane 1 cml output data, true. n10 serdout [ 0 ] + output lane 0 cml output data, true. n11 drvdd1 power serial digital power supply (1.3 v). n12 vp_byp input voltage bypass. n13, n14 drvdd2 power power supply (2.5 v) reference clock divider for syncinb , divclk . p1 drvdd1 power serial digital power supply (1.3 v). p2 serdout [ 7 ] ? output lane 7 cml output data, complement. p3 serdout [ 6 ] ? output lane 6 cml output data, complement. p4 serdout [ 5 ] ? output lane 5 cml output data, complement. p5 serdout [ 4 ] ? output lane 4 cml output data, complement. p6 drvdd1 power serializer digital power supply (1.30 v). p7 serdout [ 3 ] ? output lane 3 cml output data, complement. p8 serdout [ 2 ] ? output lane 2 cml output data, complement. p9 serdout [ 1 ] ? output lane 1 cml output data, complement. p10 serdout [ 0 ] ? output lane 0 cml output data, complement. p11 drvdd1 power serializer digital power supply (1.30 v). p12 drgnd ground digital driver ground supply. this pin connects to the digital driver ground plane. p13 divclk? output divide -by - 4 reference clock lvds, complement. p14 divclk+ output divide -by - 4 reference clock lvds, true. table 9 . pin function descriptions (by function) 1 pin no. mnemonic type description general power and ground supply pins a1 to a3, a5, a8, a11, b1 to b4, b6, b8 to b11, b13, b14, c1 to c5, c7, c9, c10, c12, c13, d5, d6, d9, d10, e6, e9, e10 , e13, e14 , f6 , f9, f10 , f13, g6 , g9, g10, g13, h6 , h9, h10 , h13, h14, j9, j10, j13 , k5 to k13 , l13, l14 agnd ground adc analog ground . these pins connect to the analog ground plane. j6 rbias_ext input reference bias. this pin requires an external 10 k resistor connected to ground. clock pins f14 clk+ input adc clock input, true. g14 clk? input adc clock input, complement. adc analog power and ground supplies pins a6, a13, a14, b7, b12, c8, c11, d8, d11, e8, e11, f8, f11, g8, g11, h8, h11, j8, j11 avdd2 power adc analog power supply (2.50 v) . a4, b5, c6, c14, d7, d12 to d14, e7, e12, f7, f12, g7, g12, h7, h12, j7, j12 avdd1 power adc analog power supply ( 1.30 v) . a12 vm_byp input voltage bypass. a1 to a3, a5, a8, a11, b1 to b4, b6, b8 to b11, b13, b14, c1 to c5, c7, c9, c10, c12, c13,d5, d6, d9, d10, e6, e9, e10 , e13, e14 , f6 , f9, f10 , f13, g6 , g9, g10, g13, h6 , h9, h10 , h13, h14, j9, j10, j13 , k5 to k13 , l13, l14 agnd ground adc analog ground . these pins connect to the analog ground plane. rev. 0 | page 12 of 56
data sheet ad9625 pin no. mnemonic type description adc analog input and outputs pins a9 vin+ input differential analog input , true . a10 vin? input differential analog input , complement . a7 vcm output analog input, common mode (0.525 v). e5 vmon output ctat voltage monitor output (diode temperature sensor). jesd204b high speed power and ground pins n1, n6, n11, p1, p6, p11 drvdd1 power serial digital power supply (1.3 v). m1 to m10, m13, m14, p12 drgnd ground digital driver ground supply. these pins connect to the digital driver ground plane. n13, n14 drvdd2 power power supply (2.5 v) reference clock divider, syncinb , divclk. m11 drvdd1 power power supply (1.3 v) reference clock divider, vco, and synthesizer. n12 vp_byp input voltage bypass. l2 dnc n/a do not connect. do not connect to th is pin . jesd204b high speed serial i/o pins j14 sysref+ input system reference chip synchronization, true. k14 sysref? input system reference chip synchronization, complement. l4 syncinb+ input synchronization, true . syncinb lvds input (active low, true). l3 syncinb? input synchronization, complement. syncinb lvds input (active low, complement). n10 serdout [ 0 ] + output lane 0 cml output data, true. p10 serdout [ 0 ] ? output lane 0 cml output data, complement. n9 serdout [ 1 ] + output lane 1 cml output data, true. p9 serdout [ 1 ] ? output lane 1 cml output data, complement. n8 serdout [ 2 ] + output lane 2 cml output data, true. p8 serdout [ 2 ] ? output lane 2 cml output data, complement. n7 serdout [ 3 ] + output lane 3 cml output data, true. p7 serdout [ 3 ] ? output lane 3 cml output data, complement. n5 serdout [ 4 ] + output lane 4 cml output data, true. p5 serdout [ 4 ] ? output lane 4 cml output data, complement. n4 serdout [ 5 ] + output lane 5 cml output data, true. p4 serdout [ 5 ] ? output lane 5 cml output data, complement. n3 serdout [ 6 ] + output lane 6 cml output data, true. p3 serdout [ 6 ] ? output lane 6 cml output data, complement. n2 serdout [ 7 ] + output lane 7 cml output data, true. p2 serdout [ 7 ] ? output lane 7 cml output data, complement. p14 divclk+ output divide -by - 4 reference clock lvds, true. p13 divclk? output divide -by - 4 reference clock lvds, complement. digital supply and ground pins d1 to d3, f1 to f3, h1 to h3, k1 to k2 dvdd1 power adc digital power supply (1.3 v). f5, g5 dvddio power digital i/o power supply (2.5 v). f4 spi_vddio power spi digital power supply (2.5 v). e4 dvdd2 power adc digital power supply (2.5 v). e1 to e3, g1 to g3, j1 to j3, l1, l5 to l 9 dgnd ground digital control ground supply. these pins connect to the digital ground plane. d4 dnc n/a do not connect. do not connect to this pin. leave this pin floating . rev. 0 | page 13 of 56
ad9625 data sheet pin no. mnemonic type description digital control pins k3 rstb input chip digital reset, active low. k4 dnc n/a do not connect. do not connect to this pin. leave this pin floating . m12 rext input external resistor, 10 k to ground. g4 csb input spi chip select cmos input. active low. h4 sclk input spi serial clock cmos input. j4 sdio i/o spi serial data cmos input/output. j5 fd output fast detect output. this pin requires an external 10 k resistor connected to ground. h5 irq output interrupt request output signal. l10 to l12 dnc n/a do not connect. do not connect to th ese pin s . leave these pins floating. 1 note that when pins are relevant to multiple categories, they are rep eated in table 9 . pins may not appear in alphanumeric order within table 9 . rev. 0 | page 14 of 56
data sheet ad9625 typical performance characteristics figure 6. fft plot at 2. 0 gsps, f in = 1807.3 mhz at a in (sfdr = 75.5 dbc, snr = 58.1 dbfs) figure 7. fft plot at 2.0 gsps, f in = 730.3 mhz at ain (sfdr = 80. 9 dbc, snr = 59.2 dbfs) figure 8. fft plot at 2. 0 gsps, f in = 310.3 mhz at a in (sfdr = 82.2 dbc, snr = 59.6 dbfs) figure 9 . snr/sfdr vs. analog input amplitude at 2 gsps, f in = 241.1 mhz at a in figure 10 . snr/sfdr vs. analog input amplitude at 2 gsps, f in = 1811.3 mhz at a in figure 11 . current and power vs. sampl e rate 0 ?120 ?100 ?80 ?60 ?40 ?20 0 1000 800 600 400 200 11814-104 amplitude (dbfs) frequency (mhz) 2000msps 1807.3mhz at ?1dbfs snr = 58.12dbfs sfdr = 75.5dbc 0 ?120 ?100 ?80 ?60 ?40 ?20 0 1000 800 600 400 200 11814-105 amplitude (dbfs) frequency (mhz) 2000msps 730.3mhz at ?1dbfs snr = 59.19dbfs sfdr = 80.9dbc 0 ?120 ?100 ?80 ?60 ?40 ?20 0 1000 800 600 400 200 11814-106 amplitude (dbfs) frequency (mhz) 2000msps 310.3mhz at ?1dbfs snr = 59.6dbfs sfdr = 82.2dbc 100 90 80 70 60 50 40 30 20 10 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 11814-108 snr/sfdr (db) amplitude (db) sfdr (dbfs) snr (dbfs) sfdr (dbc) snr (db) 100 90 80 70 60 50 40 30 20 10 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 11814-109 snr/sfdr (db) amplitude (db) sfdr (dbfs) snr (dbfs) sfdr (dbc) snr (db) 1500 0 5.0 2.0 2.5 3.0 3.5 4.0 4.5 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 300 500 700 900 1100 1300 1500 1700 1900 11814-110 current (ma) power (w) sample rate (msps) i drvdd1 i avdd2 i dvdd1 i dvdd2 , i drvdd2 total power i avdd1 rev. 0 | page 15 of 56
ad9625 data sheet figure 12 . full power bandwidth at 2.0 gsps figure 13 . two tone sfdr and imd3 vs. analog input amplitude at 2.0 gsps at 1800 mhz ain figure 14 . two tone sfdr and imd3 vs. analog input amplitude at 2.0 gsps at 230 mhz ain figure 15 . snr/sfdr vs. analog input frequency at different temperatures at 2.0 gsps figure 16 . snr/sfdr vs. sample rate figure 17 . input referred noise histogram 0 ?14 ?12 ?10 ?8 ?6 ?4 ?2 10m 100m 1g 10g 11814-111 amplitude (db) a in frequency (hz) 120 100 80 60 40 20 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 11814-112 sfdr (db) amplitude (dbfs) imd3 (dbfs) sfdr (dbfs) sfdr (dbc) 120 100 80 60 40 20 0 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 11814-215 sfdr (db) amplitude (dbfs) imd3 (dbfs) sfdr (dbfs) sfdr (dbc) 90 85 80 75 70 65 60 55 50 100 300 500 700 900 1100 1300 1500 1700 1900 11814-113 snr/sfdr (db) analog input frequency (mhz) sfdr (dbc) snr (dbfs) t a = +90c t a = +25c t a = ?55c 100 95 90 85 80 75 70 65 60 55 40 45 50 300 500 700 900 1100 1300 1500 1700 1900 11814-217 snr/sfdr (db) sample rate (msps) sfdr (dbc), 240.1mhz sfdr (dbc), 1810.3mhz snr (dbfs), 240.1mhz snr (dbfs), 1810.3mhz 5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 more n ? 4 n ? 2 n more n + 4 n + 2 11814-114 hits (millions) bins rev. 0 | page 16 of 56
data sheet ad9625 figure 18 . two tone fft plot at 2.0 gsps, f in1 = 1805.5 mhz and f in 2 = 1808.5 mhz at ain , ?7 dbfs (sfdr = 78.1 dbc) figure 19 . two tone fft plot at 2.0 gsps, f in1 = 728.5 m h z and f in 2 = 731.5 mhz at ain , ?7 dbfs (sfdr = 81 dbc) figure 20 . two tone fft plot at 2.0 gsps, f in1 = 228.5 mhz and f in 2 = 231.5 mhz at ain, ?7 dbfs (sfdr = 81 dbc) figure 21 . differential nonlinearity (dnl), 0.2 lsb figure 22 . integral nonlinearity (inl), 0. 4 lsb 0 ?120 ?100 ?80 ?60 ?40 ?20 0 1000 800 600 400 200 11814-219 amplitude (dbfs) frequency (mhz) 2000msps f in1 = 1805.5mhz at ?7.0dbfs f in2 = 1808.5mhz at ?7.0dbfs sfdr = 78.117dbc 0 ?120 ?100 ?80 ?60 ?40 ?20 0 1000 800 600 400 200 11814-220 amplitude (dbfs) frequency (mhz) 2000msps f in1 = 728.5mhz at ?7.0dbfs f in2 = 731.5mhz at ?7.0dbfs sfdr = 80.98dbc 0 ?120 ?100 ?80 ?60 ?40 ?20 0 1000 800 600 400 200 11814-221 amplitude (dbfs) frequency (mhz) 2000msps f in1 = 228.5mhz at ?7.0dbfs f in2 = 231.5mhz at ?7.0dbfs sfdr = 80.76dbc 0.5 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 ?1 4095 3071 2047 1023 11814-222 dnl (lsb) codes 0.6 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0 4096 3072 2048 1024 11814-223 inl (lsb) codes rev. 0 | page 17 of 56
ad9625 data sheet equivalent test circuits figure 23 . equivalent analog input circuit figure 24 .equivalent sclk circuit figure 25 . equivalent temperature sensor circuit figure 26 . equivalent clock input circuit figure 27 . equivalent csb input circuit figure 28 . equivalent divclk output circuit 15? 0.6pf 50 0.2pf 0.5pf 0.2pf vdd ain 11814-010 vdd 1k? vdd sclk 1 1814-0 1 1 2pf vdd 2k 1k? 1 1814-012 avdd clk+ avdd clk? 0.88v avdd 20k? 20k? 1 1814-013 11814-051 csb 1k? 11814-052 divclk rev. 0 | page 18 of 56
data sheet ad9625 theory of operation adc architecture the ad9625 is a pipelined adc. the pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on the preceding samples. sampli ng occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched capacitor digital - to - analog converter (dac) and an interstage residue amplifier (mdac). the residue am plifier magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitat e digital correction of flash errors. the last stage simply consists of a flash adc. the input stage contains a differential sampling circuit that can be ac - or dc - coupled in differential or single - ended modes. the output staging block aligns the data, corrects errors, and passes the data to the output buffers. the output buffers are powered from a separate supply, a llowing adjustment of the out put drive current. synchronization capability is provided to allow synchronized timing between multiple devices. fast detect the fast detect block within the ad9625 generates a fast detection bit (fd), which, when used with variable gain amplifier front - end blocks, reduces the gain and prevents the adc input signal levels from exceeding the converter range. figure 29 shows the rapidity by which the detection bit is programmable using an upper threshold, lower threshold, and dwell time. the fd bit is set w hen the absolute value of the input signal exceeds the programmable upper threshold level. the fd bit clears only when the absolute value of the input signal drops below the lower threshold level for greater than the programmable dwell time, thereby providing hysteresis and preventing the fd bit from excessive toggling. gain threshold opera tion the threshold prohibits background calibration updates for small signal amplitudes. the threshold for gain calibration is enabled by defau lt . threshold operation the absolute value of every sample is accumulated to produce an average voltage estimate. when the calibration has run for its predetermined number of samples, the voltage estimate is compared to the data set threshold . if the vol tage estimate is greater than the threshold, the cali - bration coefficients update; otherwise, no update occurs. threshold format the threshold registers are all 16 - bit registers loaded via the spi one byte at a time. the threshold values range from 0 to 1 6,384, corresponding to a voltage range of 0.0 v to 1. 1 v (full scale). the calibration threshold range is 0 to 16,384 (0x00 to 0x4000 , hexadecimal ) and represents the average magnitude of the input. for example, to set the threshold so that a ? 6 dbfs inp ut sine wave sit s precisely at the threshold requires a threshold setting of 16,384 20 6 10 ? 2 5228 figure 29 . fast detection bit upper threshold lower threshold fd dwell time timer reset by rise above lt timer completes before signal rises above lt dwell time 1 1814-016 rev. 0 | page 19 of 56
ad9625 data sheet test modes figure 30 . test modes table 10 . flexible output test modes from spi register 0x0 0 d output test mode bit sequence pattern name digital output word 1 (default twos complement format) digital output word 2 (default twos complement format) subject to data format select 0000 off (default) not applicable not applicable yes 0001 midscale short 0000 0000 0000 = word1 yes 0010 positive f ull scale 0 111 1111 1111 = word1 yes 0011 negative f ull scale 1 000 0000 0000 = word1 yes 0100 alternating c heckerboard 1010 1010 1010 0101 0101 0101 no 0101 pn sequence long not applicable not applicable yes 0111 one - /zero - word toggle 1111 1111 1111 0000 0000 0000 no 1000 user test mode user data from register 0x 0 19 to register 0x 0 20 user data from register 0x 0 19 to register 0x 0 20 yes 1111 ramp output n n + 1 no adc core framer seralizer output jesd204b test patterns 10 bit spi register 0x061 bits 5:4 = 01 and bits 3:0 0000 jesd204b test patterns 16 bit spi register 0x061 bits 5:4 = 00 and bits 3:0 0000 jesd204b sample construction adc test patterns 12 bit spi register 0x00d bits 3:0 0000 tail bits frame construction 8b/10b encoder scrambler (optional) 11814-018 rev. 0 | page 20 of 56
data sheet ad9625 digital downconverte rs ( ddc) figure 31 . digital downconverters the ad9625 architecture includes tw o ddcs , each designed to extract a portion of the full digital spectrum captured by the adc. each tuner consists of an independent frequency synthesizer and quadrature mixer; a chain of low - pass filters for rate conversion follows these components. assuming a sampling frequency of 2.000 ghz, the frequency synthesizer (10 - bit nco) allow s for 1024 discrete tuning frequencies, ranging from ?0.999 ghz to +1.000 ghz, in steps of 2000/1024 = 1.953 mhz . the low - pass filters allow for two modes of decimation. ? a high bandwidth mode, 192 mhz wide (from ?96 mhz to +96 mhz), sampled at 2.0 ghz/8 = 250 mhz for the i and q branches separately. the 16 - bit samples from the i and q branches are transmitted through a dedicated jesd204b interface. ? a low bandwidth mode, 96 mhz wide (from ? 48 mhz to +48 mhz), sam pled at 2.0 ghz/16 = 125 mhz for the i and q branches separately. the 16 - bit samples from the i and q branches are transmitted through a dedicated jesd204b interface. by design, all of the blocks operate at a single clock frequency of 2.0 ghz/8 = 250 mhz. each filter stage includes a gain control block that is programmable by the user. the gain varies from 0 db to 18 db, in steps of 6 db, and the gain is applied before final scaling and rounding. the gain control feature may be useful in cases where the tuner filters out a strong out - of - band interf erer, leaving a weak in - band signal. frequency synthesize r and mixer for a sampling rate of 2.000 ghz, the synthesizer (10 - bit nco) outputs one of 1024 possible complex frequencies from ? 0.999 ghz to +1.000 ghz. the synthesizer employs the direct digital s ynthesis technique, using look - up sine tables and a phase accumulator. the user specifies the tuner frequency by writing to a 10 - bit phase increment register. high bandwidth decim ator the first filter stage is designed for a rate reduction factor of 8, y ielding a sample rate of 2.000 ghz/8 = 250 mhz. to achieve a combination of low complexity and low clock ra te, the ddc employs a decimate - by - 8 polyphase fuse filter that receives eight 13- bit samples from the mixer block at every clock cycle. the block de sign provides user specified gain control, from 0 db to 18 db in steps of 6 db. the gain is applied before final scaling and rounding to 16 bits. figure 32 . magnitude response of the decimate - by - 8 polyphase fuse filter filter pe rformance is shown in figure 32 an d figure 34 . the filter yiel ds an effective bandwidth of 96 mhz, with a transition band of 125 ? 96 = 29 mhz. hence, the two - sided complex bandwidth of the filter is 192 mhz. a rejection ratio of 85 db ensures that the seven aliases that fold back into the pass band yield an snr of 85 db ? 10log10 (7) = 76.5 db, which ensures that the aliases remain sufficiently below the noise floor of the input signal. the pass - band ripple is 0.05 db, as shown in figure 33 . synthesizer nco 12-bit adc @ 2.0gsps decimation by 8 gain select: 0db, 6db, 12db, 18db mode select: 96mhz or 192mhz bw mixer mixer 8 12-bit @ 250mhz decimation by 8 decimation by 2 8 13-bit @ 250mhz 8 12-bit @ 250mhz 8 13-bit @ 250mhz 16-bit @ 250mhz 16-bit @ 125mhz 16-bit @ 125mhz i-phase 16-bit @ 250mhz q-phase tuner select: ?1.0ghz to +1.0ghz gain select: 0db, 6db, 12db, 18db to framer to framer 1 1814-019 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 0 ?10 f s /2 magnitude (db) frequency (mhz) 1 1814-020 rev. 0 | page 21 of 56
ad9625 data sheet rev. 0 | page 22 of 56 figure 33. magnitude ripple in the pass band low bandwidth decimator use the second filter stage in the optional low bandwidth mode only. it achieves an additional rate reduction factor of 2, yielding a final sample rate of 2.000 ghz/16 = 125 mhz. the internal architecture of the low bandwidth decimation filter is similar to that of a high bandwidth decimator. moreover, for ease of physical design, the block operates at 250 mhz, a result of which both the i- and q-phases can share the filter engine. the performance of the low bandwidth decimation filter is shown in figure 34 and figure 35. the filter yields an effective bandwidth of 60 mhz, with a transition band of 81.25 mhz ? 60 = 21.25 mhz. thus, the two sided, complex bandwidth of the filter is 120 mhz. a rejection ratio of 85 db ensures that the alias region folds back well below the noise floor of the input signal. as with the high bandwidth filter, this block provides user specified gain control, from 0 db to 18 db, in steps of 6 db. the gain is applied before final quantization at the output of the low bandwidth decimation filter to 16 bits. figure 34. magnitude response of decimate-by-2 filter figure 35. magnitude ripple in the pass band 0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0120 100 80 60 40 20 magnitude (db) frequency (mhz) 11814-021 10 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0160 140 120 100 80 60 40 20 magnitude (db) frequency (mhz) 11814-022 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 060 50 40 30 20 10 magnitude (db) frequency (mhz) 11814-023
data sheet ad9625 analog input conside rations figure 36 . front - end minimum requirement series resistors (r5 and r6) are recommended to reduce bandwidth peaking and minim ize kickback from the adc sampling capacitor . small ser ies resistors (r3 and r4) limit bandwidth, but can be installed to further improve performance. table 11 lists the front - end requirements. table 11. recommended front -e nd co mponents components component value r1 50 (termination) r2 50 (termination) r3 0 to 33 r4 0 to 33 r5 0 to 33 r6 0 to 33 clock input consider ations for optimum performance, the ad9625 sample clock inputs (clk+ and clk ? ) should be driven with a differential signal. this s ignal is typically ac - coupled to the clk+ and clk? pins via a transformer or capacitors. these pins are biased internally and require no additional bias ing . clock jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input frequency ( f a ) due only to aperture jitter ( t j ) can be calculated by snr = 20 log 10(2 f a t j ) in this equation, the rms aperture jitter represents the root - mean - square of all jitter sources, including the clock input, analog input signal, and adc aperture jitter specifications. if undersampling ap plications are particularly sensitive to jitter (see figure 37). dc coupling the ad9625 cannot operate correctly by dc coupling the analog inputs , vin . it is recommended that the analog inputs are ac - coupled around a common - mode voltage , vcm, using a front - end network , as shown in figure 36. figure 37 . ideal snr vs. analog input frequency and jitter i n cases where ap erture jitter may affec t the dynamic range of the ad9625 , treat t he clock input as an analog signal . t o avoid modulating the clock signal with digital noise , separate p ower supplies for clock drivers from the adc output driver supplies . if the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. refer to the an - 501 application note and the an - 756 application note for more information about jitter per formance as it relates to adcs. clock duty cycle considerations typical high speed adcs use both clock edges to generate a variety of internal timing signals. as a result, these adcs may be sensitive to clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. calibration the ad9625 requires a calibration c ycle at startup and once every 24 - hour period. to perform this calibration at startup, the default value in register 0x12a[7:0] must be overwritten and set to 0x03 at adc startup to initiate the calibration. when the calibration is initiated, the adc needs to remain in this mode for at least 500 clock cycles. during calibration, the output data of the adc is invalid. when the calibration is complete, a successive write of register 0x12a[7:0] to 0x01 terminates the calibration and valid adc data resumes. to maintain adc performance, repeat this calibration cycle once in every 24 - hour period. ad9625 avddx vcm drvddx r5 r6 r3 r4 0.1f 0.1f r1 r2 1 1814-024 1 10 100 1000 30 40 50 60 70 80 90 100 110 120 130 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps 10 bits 16 bits 14 bits 12 bits 8 bits rms clock jitter requirement snr (db) analog input frequency (mhz) 11814-240 rev. 0 | page 23 of 56
ad9625 data sheet digital outputs introduction to jesd 204b interface the ad9625 digital output complies with the jedec standard no. jesd204b, serial interface for data converters . jesd204b is a protocol to link the ad9625 to a digital processing device over a serial interface up to 6.5 gbps link speeds. the benefits of the jesd204b interface over lvds include a reduction in required board area for data interface routing, and enabling smaller packages for converter and logi c devices. the ad9625 supports one, two, four, six , or eight output lanes. the jesd204b data transmit block assembles the parallel data from the adc into frames and uses 8 - bit /10 - bit encoding as w ell as optional scrambling to form serial output data. lane synchronization is supported using special characters during the initial establishment of the link , and additional data that is used to maintain synchronization is embedded in the data stream ther eafter. a jesd204b receiver is required to complete the serial link. for additional details on the jesd204b interface, users are encouraged to refer to the jesd204b standard. the ad9625 jesd204b t ransmit block maps to two digital down converters for t he outputs of the adc over a link. a link can be configured to use up to eight jesd204b lanes. the jesd204b specification refers to a number of parameters to define the link , and these parameters must match between the jesd204b transmitter ( ad9625 output) and receiver (fpga, asic, or logic device). table 12 describes the jesd204b interface nomenclature (the terms, converter device and link, are used interchangeably in the specification). table 12 . jesd204b interface nomen clature symbol description s samples transmitted per single converter per frame cycle m number of converters per converter device (link) l number of lanes per converter device (link) n converter resolution n ' total number of bits per sample cf number of control words per frame clock cycle per converter device (link) cs number of control bits per conversion sample k number of frames per multiframe hd high density mode f octets per frame c control bit (overrange, time stamp) t tail bit the ad9625 adheres to the jesd204b draft specification , which provides a high speed , serial, embedded clock interface standard for data converters and logic devices. it is designed as a n mcda - ml, subcla ss 1 d evice that u s es the sysref input signal for multi chip synchronization and deterministic latency . this design adheres to the following basic jesd204b link config - uration parameters: ? m = 1 (single converter , always for ad9625 ) ? l = 1 to 8 ( up to eight lanes) ? s = 4 (four samples per jesd204b frame) ? f = 1 , 2, 4, 8 ( up to 8 octet s per frame) ? n ' = 12, 16 (12 - or 16 - bit jesd204b word size) ? hd = 0, 1 (high density mode , sample span multiple lanes) functional overview the block diagram in figure 38 shows the flow of data through the jesd204b hardware from the sample input to the physical output. the processing c an be divided into layers that are derived from the osi model widely used to describe the abstraction layers of communications systems. these are the transport layer, data link layer, and physical layer (serializer) . each of these layers are described in d etail in the following sections . transport layer the transport layer handles packing the data ( consist ing of sa mples and optional control bits) into 8 - bit words that ar e sent to the data link layer. the transport layer is controlled by rules derived from t he link configuration d ata. it pack s data according to the rules , adding tail bits to fill gaps when required. data link layer the data link layer is responsible for the low level functions of passing data across the link. these include optionally scrambli ng the data, handling the synchronization process for characters, frames, and lanes across the links, encoding 8 - bit data - words into 10 - bit characters, and inserting appropriate control characters into the data output. t he data link layer is also responsib le for sending the initial lane alignment sequence (ilas) , which contains the link configuration data , used by the receiver ( rx ) to verify the settings in the transport laye r. physical layer the physical layer consists of the high speed circuitry clocked at the serial clock rate . the p hysical layer includes the serialization circuits and the high speed drivers. figure 38 . data flow sample construction frame construction scrambler alignment character generation 8-bit/10-bit encoder crossbar mux serializer output processed samples from adc data link layer transport layer physical layer 11814-242 rev. 0 | page 24 of 56
data sheet ad9625 jesd204b link establ ishment the ad9625 jesd204b tx interface operates in subclass 1 as defin ed in the jedec standard no. 2 04b - july 2011 specification . it is divided into t he following steps: code group synchronization, initial lan e alignment sequence, and data streaming. code group synchronization (cgs) and syncinb cgs is the process where the jesd204b receiver finds the boundaries between the 10 - bit characters in the stream of data. during the cgs phase, the jesd204b transmit blo ck transmits / k28.5 / characters. the receiver (external logic device) must locate the / k28.5 / characters in its input data stream using clock and data recovery (cdr) techniques. the receiver issues a synchronization request by activating the syncinb pin s of the ad9625 . the jesd 204b tx begin s sending /k 28.5 / characters until the next lmfc boundary. when the receiver has synchronized, it waits for the correct reception of at least four consecutive /k 28.5 / symbols. it then deactivates syncinb . the ad9625 then transmit s an initial lane alignment sequence (ilas) on the following lmfc boundar y. for more information on the code group synchroni zation phase, please refer to the jedec standard no. 204b - july 2011 , s ection 5.3.3.1. the syncinb pin operation can be controlled by spi. the syncinb signal is a differential lvds mode signal by default, but it can also be driven single ended. for more i nformation on configuring the syncinb pin operation, refer to the memory map section . initial lane alignment sequence (ilas) the ilas phase follows the cgs phase and begin s on the next lmfc boundary. the ilas consists of four mulitframes, with an /r/ character marking the beginning and an /a/ character marking the end. the ilas begins by sending an /r/ character followed by 0 to 255 ramp data for one multiframe. on the second multiframe , the link configuration data is sent starting with the third character. the second character is a /q/ character to confirm that the link configuration data follow s . all undefined data slots ar e filled with ramp data. the ilas sequence is never scrambled. the ilas sequence construction is shown in figure 41 . the four multiframes include the following: ? multiframe 1: b egins with an /r/ character ( k28.0 ) and ends with an /a/ character ( k28.3 ). ? multiframe 2: b egins with an /r/ character followed by a /q / [ k28.4] character, followed by link configuration parameters over 14 configuration octets and ends with an /a/ c haracter. many of the parameter values are of the notation of the value , ? 1. ? multiframe 3: this i s the same as multiframe 1. ? multiframe 4: this i s the same as multiframe 1. data streaming after the initial lane alignment sequence is complete, the user data is sent. i n a usual frame , all characters are user data . h owever , to monitor the frame clock and multiframe clock synchronization, there is a mechanism for replacing characters with /f/ or /a/ alignment characters when the data meets certain c onditions . these conditions are differe nt for unscrambled and scrambled data . the scrambling operation is enabled by default but may be disabled using spi. for scrambled data , any 0xfc character at the end of a frame is replaced by an /f/ , and any 0xfd character at the end of a multiframe is re placed with an /a/. the jesd204b rx check s for /f/ and /a/ characters in the received data stream and verif ies that they only occur in the expected locations. if an unexpected /f/ or /a/ character is found, the receiver handle s the situation by using dynam ic realignment or a ctivating the syncinb signal for more than four frames to initiate a resynchronization. for un scrambled data, if the final character of two subsequent frames is equal, the second character is replaced with an /f/ if it is at the end of a frame, and an /a/ if it is at the end of a multiframe . insertion of alignment characters may be modified using spi. the frame alignment character insertion is enabled by default. more information on the link controls is available in the memory map section , register 0x062 . 8- bit/10 - bit encoder the 8 -b it /10 -b it e ncoder converts 8 - bit octets int o 10 - bit characters and inserts control characters into the stream when needed. the control characters used in jesd204b are shown in table 13 . the 8 -b it /10 -b it encoding allows the signal to be dc balanced by using the same number of ones a nd zeros. the 8-b it /10 -b it interface has options that may be controlled via spi. these operations include bypass, invert or mirror. these options are intended to be a troubleshooting tool for the verification of the digital front end (dfe). digital outputs, timing , and controls the ad9625 p hysical l ayer consists of drivers that are defined i n the j edec standard no. 204b - july 2011. the d ifferential d igital outputs a re p owered up b y d efault. t h e d rivers u s e a dy namic 100 i nternal te rmination to r educe u nwanted r eflections. p lace a 100 ? differential termination resistor at each receiver input to result in a nominal 300 mv p- p swing at the receiver (see figure 39 ). alternatively, single - ended 50 ? termination can be used. when single - ended termination is used, the termi - nation voltage should be drvdd/2; otherwise, 0.1 f ac coupling capacitors can be used to terminate to any single - ended voltage. rev. 0 | page 25 of 56
ad9625 data sheet figure 39 . ac - coupled digital output termination example the ad9625 digital outputs can interface with custom asics and fpga receivers, providing superior switching performance in noisy environments. single point - to - point network topologies are recommended with a single differential 100 termination resistor placed as close to the receiver inputs as possi ble. the common mode of the digital output automatically biases itself to half the drvdd supply . see figure 40 for dc coupling the outputs to the receiver logic. figure 40 . dc - coupled digital output termination example if there is no far end receiver termination, or if there is poor differential trace routing, timing errors may result. to avoid such timing errors, it is recommended that the trace length be less than six inches, and that the differential output traces be close together and at equal lengths. de - emphasis de - emphasis enables the receiver eye diagram mask to be met in conditions where the interconnect insertion loss does not meet the jesd204b specification. the de - emphasis feature should only be used when the receiver is unable to recover the clock due to excessive insertion loss. under normal conditions , it is disabled to conserve power. a dditionally , enabling and setting too hig h a de - emphasis value on a short link may cause the receiver eye diagram to fail. u s e the de - emphasis setting with caution because it may increase emi. see the memory map section for details. figure 41 . initial lane alignment sequence table 13. ad9625 control characters u sed in jesd204b abbreviation control symbol 8 - bit value 10 - bit value rd (running disparity) = ?1 10 - bit value rd (running disparity) = +1 description /r/ / k28.0 / 000 11100 001111 0100 110000 1011 start of multiframe / a / / k28.3 / 011 11100 001111 0011 110000 1100 lane alignment / q / / k28.4 / 100 11100 001111 0100 110000 1101 start of link configuration data / k / / k28.5 / 101 11100 001111 1010 110000 0101 group synchronization / f / / k28.7 / 111 11100 001111 1000 110000 0111 frame alignment 11814-244 serdout[x]+ drvdd serdout[x]? output swing = 300mv p-p 100 receiver v cm = drvdd/2 100 differential trace pair 11814-243 or serdoutx+ drvdd v rxcm serdoutx? output swing = 300mv p-p 0.1f 100 50 50 0.1f receiver v cm = v rxcm 100 differential trace pair k k r d d a r d d a r d d a d d a r q c c d end of mul tiframe st art of user d at a st art of link configur a tion dat a st art of ilas 1 1814-132 rev. 0 | page 26 of 56
data sheet ad9625 table 14 . jesd204b mode of operation ( m = 1, s = 4, n ' = 16 , unless otherwise noted ) quick config uration value description 1 lanes (l) octets/frame (f) sample clock rate sample clock multiplier jesd204b lane rate min imum msps max imum msps min imum mbps max imum mbps 0x02 generic 2 4 330 650 10 3300 6500 0x04 generic 4 2 650 1300 5 3250 6500 0x06 generic (n ' = 12) 6 1 1300 2000 2.5 3250 5000 0x08 generic 8 1 1300 2000 2.5 3250 5000 0x18 f s 8 2 4 406 813 8 3250 6500 0x28 f s 4 4 2 813 1625 4 3250 6500 0x48 f s 2 8 1 1625 2000 2 3250 4000 0x81 single ddc , high bw 1 8 650 1300 5 3250 6500 0x82 single ddc, high bw 2 4 1300 2000 2.5 3250 5000 0x91 single ddc , low bw 1 8 1300 2000 2.5 3250 5000 0xc1 dual ddc , high bw 1 8 330 650 10 3300 6500 0xc2 dual ddc , high bw 2 4 650 1300 5 3250 6500 0xc4 dual ddc , high bw 4 2 1300 2000 2.5 3250 5000 0xd1 dual ddc , mixed bw 1 8 330 650 10 3300 6500 0xd2 dual ddc , mixed bw 2 4 650 1300 5 3250 6500 0xe1 dual ddc , mixed bw 4 2 1300 2000 2.5 3250 5000 0xe2 dual ddc , low bw 1 8 650 1300 5 3250 6500 0xe4 dual ddc , low bw 2 4 1300 2000 2.5 3250 5000 1 ddc means digital downconverter , bw means bandwidth, f s x means sample rate multiplied by an integer. table 15. jesd204b logical lane mapping quick configuration value description lanes (l) logical lane 0 logical lane 1 logical lane 2 logical lane 3 logical lane 4 logical lane 5 logical lane 6 logical lane 7 0x02 generic 2 s[n], s[n + 1] s[n + 2], s[n + 3] off off off off off off 0x04 generic 4 s[n] s[n + 1] s[n + 2 ] s[n + 3] off off off off 0x06 generic (n ' = 12) 6 s msb [n], s lsb [n], s msb [n + 1], s lsb [n + 1], s msb [n + 2], s lsb [n + 2], s msb [n + 3], s lsb [n + 3] off off 0x08 generic 8 s msb [n] s lsb [n] s msb [n + 1] s lsb [n + 1] s msb [n + 2] s lsb [n + 2] s msb [n + 3] s lsb [n + 3] 0x18 f s 8 2 see figure 46 , f s 2 mode application layer (transmit) 0x28 f s 4 4 see figure 46 , f s 2 mode application layer (transmit) 0x48 f s 2 8 s msb [n], s lsb [n], s msb [n + 1], s lsb [n + 1], s msb [n + 2], s lsb [n + 2], s msb [n + 3], s lsb [n + 3], s msb [n + 4], s lsb [n + 4]; see figure 46 , f s 2 mode application layer (t ransmit) 0x81 single ddc , high bw 1 i 0 [n], q 0 [n], i 0 [n + 1], q 0 [n + 1] off off off off off off off 0x82 single ddc , high bw 2 i 0 [n], q 0 [n] i 0 [n+1], q 0 [n+1] off off off off off off 0x91 single ddc , low bw 1 i 0 [n], q 0 [n], i 0 [n + 1], q 0 [n + 1] off off off off off off off 0xc1 dual ddc , high bw 1 i 0 [n], q 0 [n], i 1 [n], q 1 [n] off off off off off off off 0xc2 dual ddc , high bw 2 i 0 [n], q 0 [n] i 1 [n], q 1 [n] off off off off off off 0xc4 dual ddc , high bw 4 i 0 [n] q 0 [n] i 1 [n] q 1 [n] off off off off 0xd1 dual ddc , mixed bw 1 i 0 [n], q 0 [n], i 1 [n], q 1 [n] off off off off off off off 0xd2 dual ddc , mixed bw 2 i 0 [n], q 0 [n] i 1 [n], q 1 [n] off off off off off off rev. 0 | page 27 of 56
ad9625 data sheet quick configuration value description lanes (l) logical lane 0 logical lane 1 logical lane 2 logical lane 3 logical lane 4 logical lane 5 logical lane 6 logical lane 7 0xe1 dual ddc , mixed bw 4 i 0 [n] q 0 [n] i 1 [n] q 1 [n] off off off off 0xe2 dual ddc , low bw 1 i 0 [n], q 0 [n], i 1 [n], q 1 [n] off off off off off off off 0xe4 dual ddc , low bw 2 i 0 [n], q 0 [n] i 1 [n], q 1 [n] off off off off off off rev. 0 | page 28 of 56
data sheet ad9625 rev. 0 | page 29 of 56 physical layer output figure 42. recovered data eye of jesd204b lane at 6.25 gbps figure 43. bathtub plot of jesd204b output at 6.25 gbps figure 44. time interval histogram error of jesd204b output at 6.25 gbps scrambler the scrambler polynomial is 1 + x 14 + x 15 . the scrambler enable bit is located in register 0x06e[7]. ? setting bit 7 to 0 disables the scrambler. ? setting bit 7 to 1 enables the scrambler. tail bits the tail bit, pn generator, is located in register 0x05f[6]. ? setting bit 6 to 0 disables the tail bit generator. ? setting bit 6 to 1 enables the tail bit generator. ddc modes (single and dual) the ad9625 contains two separate ddcs that can digitally downconvert real adc output data into i/q decimated data at a reduced bandwidth. this feature is useful when the full bandwidth supplied by the 2.0 gsps converter is not needed. figure 45 shows a simplified block diagram of the ddc blocks as they traverse through the ad9625 . because all jesd204b frames contain four samples (s = 4), the output from the ddcs must also output four samples. table 16 shows the remapping of i/q samples to converter samples for the jesd204b interface, specific to the ad9625. when in mixed bandwidth mode, ddc 0 is always in high bandwidth mode and ddc 1 is always in low bandwidth mode. to match the data throughput of the high bandwidth mode, the low bandwidth samples are repeated twice in mixed bandwidth mode. table 17 lists the four frames of data for both ddc 0 (high bandwidth mode) and ddc 1 (low bandwidth mode). 400 ?400 ?300 ?200 ?100 0 100 200 300 ?150 ?100 ?50 0 50 100 150 voltage (mv) time (ps) 11814-026 1 1 ?2 1 ?4 1 ?6 1 ?8 1 ?10 1 ?12 1 ?14 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 be r ui 11814-027 180 160 140 120 100 80 60 40 20 0 ?15 ?10 ?5 0 5 10 15 hits time (ps) 11814-028
ad9625 data sheet figure 45 . ddc mapping table 16. ddc remap i/q to converter samples application mode sample[n] sample[n + 1] sample[n + 2] sample[n + 3] single ddc i 0 [n] q 0 [n] i 0 [n + 1] q 0 [n + 1] dual ddcs i 0 [n] q 0 [n] i 1 [n] q 1 [n] table 17. ddc mix ed bandwidth mode jesd204b frame number sample[n] sample[n + 1] sample[n + 2] sample[n + 3] frame 0 i 0 [n] q 0 [n] i 1 [n] q 1 [n] frame 1 i 0 [n + 1] q 0 [n + 1] i 1 [n] q 1 [n] frame 2 i 0 [n + 2] q 0 [n + 2] i 1 [n + 1] q 1 [n + 1] frame 3 i 0 [n + 3] q 0 [n + 3] i 1 [n + 1] q 1 [n + 1] checksum the jesd204b checksum value is sent with the configuration parameters during the initial lane alignment sequence. disabling the checksum is primarily for debug purposes only. 8 - bit /10 - bit encoder c ontrol the 8 - b it /10 - b it encoder must be controlled in the following manner : ? the b ypass 8 - b it /10 - b it encoder is controlled by register 0x60, bit 2 (0 = 8 - b it /10 - b it enabled; 1 = 8 - b it /10 - b it bypassed). ? the i nvert 10 - b it encoder is controlled by register 0x 0 60, bit 1 (0 = n ormal; 1 = i nvert). ? the m irror 10 - b it encoder is controlled by register 0x 0 60, bit 0 (0 = n ormal; 1 = m irrored). the inversion of the 10 - b it values allows the user to swap the true/complement differential pins swapped on the boards. for details about register 0x 0 60, see the memory map register section. initial lane alignme nt sequence (ilas) the ad9625 must support three different ilas m odes that are controlled using bits [3:2] in register 0x05f as follows: ? 00: d isabled ? 01: e nabled ? 10: r eserved ? 11: always on test mode when enabled, the device must also support the capability to repeat the ilas using bits[7:0] in register 0x062 to determine the number of times ilas is repeated (0 = repeat 0 times, ilas run s on e time only , 1 = repeat one time , ilas run s twice, and so forth ). because the number of frames per multiframe is determined by the value of k, the total number of frames transmitted during the initial lane alignment sequence is 4 ( k + 1) ( ilas_count + 1) where t he value of k is defined in register 0x070, bits[4:0]. note tha t o nly values divisible by four can be used. for details about register 0x05f and register 0x062, see the memory map register section. lane synchronization l ane s ynchronization is defined by r egister 0x05f , bit 4 (0 = disab led, 1 = enabled) . for more information, see the memory map register section. i0 q0 i1 q1 logical lane 0 (l0) logical lane 1 (l1) logical lane 2 (l2) logical lane 3 (l3) 16 16 16 16 logical lane 4 (l4) logical lane 5 (l5) logical lane 6 (l6) logical lane 7 (l7) remap i/q to converter samples sample [n] sample [n + 1] sample [n + 2] sample [n + 3] 48 adc jesd204x interface (m = 1; l = 8; s = 4; f = 1; n = 16; n' = 16; cf = 0; scr = 0, 1; hd = 1; k = see specs) 12-bit adc samples [n] through [n + 3] 1 1814-029 dcc 0 dcc 1 rev. 0 | page 30 of 56
data sheet ad9625 adc output c ontrol bits on jesd204b s amples when n ' = 16 and the adc resolution is 12, there are four spa re bits available per sample. two of these spare bits can be used as control bits in location 2 to location 1 of the sample , depending on the configuration options. the control bits are set in r egister 0x072 , bits [7:6]. ? 00: n o control bits sent per sample (cs = 0) . ? 01: one control bit sent per sample , overrange bit enabled, (cs = 1). ? 1 0 : two control bits sent per sample , overra n ge + time stamp ed sysref control bit (marks the sample of a risin g edge seen on the sysref pin) , (cs = 2). use of the sysref c ontrol b it (cs = 2) time stamps a particular analog sample that is seen coincident with a r ising signal on the sysref pins . bits[5:4] in r egister 0x061 control the jesd204b interface test injection points. ? 00: 16- bit test generation data injected at the sample input to the link . ? 01: 1 0 - bit test generation data injected at the output of the 8 - b it /10 - b it encoder (at the input to phy) . ? 10: 8 - bit test generation data injected at the i nput of the s crambler . ? 11: r eserved . bits[3:0] in register 0x061 determine the type of test patterns that are injected, as follows: ? 0000: normal operation (test mode disabled). ? 0001: alternating checker board. ? 0010: 1/0 word toggle. ? 0011: pn seque nce: l ong (x 23 + x 18 + 1) . ? 0101: continuous/repeat user test mode; most significant bits from 16 - bit user pattern (1, 2, 3, 4) are placed on the output for one clock cycle and then repeated. (output user pattern: 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4, .) ? 0110: single user test mode ; most significant bits from the 16- bit user pattern (1, 2, 3, 4) placed on the output for one clock cycle and then output s all zeros. (output user pattern : 1, 2, 3, 4, then output all zeros.) ? 0111: ramp o utput (dependent on test injection point and number of bits , n). ? 1000: m odified rpat test sequence . ? 1001: u nused . ? 1010: jspat test sequence . ? 1011: jtspat tes t sequence . ? 1100 to 1111: unused . jesd204b application layers the ad9625 supports the following application layer modes via register 0x 0 63[3:0] : ? 0100: f s x mo de which supports line rates at integer multiples of the sample rates ? 1000: single ddc mode, high bandwidth mode (only ddc 0 used) ? 1001: single ddc mode, low bandwidth mode (only ddc 0 used) ? 1010 to 1011: unused ? 110 0: dual ddc mode, high bandwidth mode (b oth ddc 0 and ddc 1 used) ? 1101: dual ddc mode, low bandwidth mode (both ddc 0 and ddc 1 used) ? 1110: dual ddc mode, mixed bandwidth mode ( ddc 0 high bandwidth mode, ddc 1 low bandwidth mode, samples repeated) f s 2, f s 4, f s 8 modes the jesd204b low multiplier mode application layer adds a rate conversion on top of a jesd204b transmitter/receiver with t he following configuration parameters: m = 1 ; l = 8 ; s = 4 ; f = 1; n = 16; n ' = 16 ; cs = 0 ; cf = 0 ; scr = 0 , 1 ; hd = 1 ; k = reference jesd204b specification. in this mode, there are five actual samples per frame and scrambling can be optionally enabled in the jesd204b interface. the transmit portion of the low multiplier mode jesd204b application layer is shown in figure 46. the first step in this application layer is where 12 - bit adc samples are divided into six bytes. to allow the line rate of the jesd204b interface to map directly into an intege r of the converter sample rate, a four to five rate conversion takes place to group the 12 - bit adc s ample s into blocks of five samples. during this rate conversion, for every five 12 - bit adc sample , an extra user defined , 4 - bit n ibble is appended to create a 64 - bit frame . next, the 64- bit low multiplier frame maps into the four 16 - bit jesd204b samples. the most significant 16 - bits of the 64 - bit low multiplier frame map to the oldest 16 - bit jesd204bsample and the least significant 16 - bits of the 64 - bit low m ultiplier frame map to the most recent 16 - bit jesd204b sample. the receive portion of th e f s 2 j esd204b a pplication l ayer is shown in figure 47. rev. 0 | page 31 of 56
ad9625 data sheet figure 46 . f s 2 mo de application layer (transmit) adc sample n (12 bits) adc jesd sample n (16 bits) application layer data link, transport, and phy layers f s 2 application layer (transmit) 4/5 rate exchange adc converter sample n (n = 8, 10, or 12 bits) control bits for sample n (cs = 0, 2 or 4 bits) adc converter sample n + 1 (n = 8, 10 or 12 bits) control bits for sample n + 1 (cs = 0, 2 or 4 bits) adc converter sample n + 2 (n = 8, 10 or 12 bits) control bits for sample n + 2 (cs = 0, 2 or 4 bits) adc converter sample n + 3 (n = 8, 10 or 12 bits) control bits for sample n + 3 (cs = 0, 2 or 4 bits) lane 0 s[n][15:0] s[n + 1][15:0] s[n + 2][15:0] s[n + 3][15:0] lane 1 lane 2 lane 3 lane 4 lane 5 lane6 lane 7 user defined (fsync[3:0]) adc sample n + 1 (12 bits) adc sample n + 2 (12 bits) adc sample n + 3 (12 bits) 48 bits @ f s /4 64 bits @ f s /5 64 bits @ f s /5 adc sample n (12 bits) adc sample n + 1 (12 bits) adc sample n + 2 (12 bits) adc sample n + 3 (12 bits) adc sample n + 4 (12 bits) (4 bits) s[n][11:0], s[n + 1][11:8] (16 bits) s[n + 1][7:0], s[n + 2][11:4] (16 bits) s[n + 2][3:0], s[n + 3][11:0] (16 bits) s[n + 4][11:0], ud[3:0] (16 bits) jesd sample n + 1 (16 bits) jesd sample n + 2 (16 bits) jesd sample n + 3 (16 bits) jesd204b framer + phy (m = 1; l = 8; s = 4; f = 1; n = 16; n' = 16; cf = 0; scr = 0, 1; hd = 1; k = see spec 1 1814-032 rev. 0 | page 32 of 56
data sheet ad9625 figure 47 . f s 2 application layer (receive) frame alignment char acter insertion frame alignment character insertion (faci) i s defined in the register map (see the memory map register section). disable faci only when it is used as a test feature. the faci disable bit is located in r egister 0x 0 5f , bit 1. use the following settings: ? setting bit 1 to 0 = faci e nabled ? setting bit 1 to 1 = faci d isabled thermal considerat ions because of the high power nature of the device , it is critical to provide airflow and/or install a heat sink when operating at a high temperature. this ensures that the maximum case temperature does not exceed 85 c. power supply conside rations the ad9625 must be powered by the following two supplies: avdd1 = dvdd1 = drvdd1 = 1.3 v , avdd2 = dvdd2 = drvdd2 = 2.5 v. an optional dvddio and spi_dvddio may be required at 2.5 v. for applications req uiring an optimal high power efficiency and low noise performance, it is recommended that adp2386 switching regulator is used to convert the 12 v input rail into two intermediate rails (2.1 v and 3.6 v). these i ntermediate rails are then postregulated by very low noise, low dropout (ldo) regulators ( adp1740 , adp7104 , and adp125 ). figure 48 shows the recommended method. application layer data link, transport, and phy layers f s 2 application layer (receive) 4/5 rate exchange customer application adc converter sample n (n = 8, 10, or 12 bits) control bits for sample n (cs = 0, 2 or 4 bits) adc converter sample n + 1 (n = 8, 10 or 12 bits) control bits for sample n + 1 (cs = 0, 2 or 4 bits) adc converter sample n + 2 (n = 8, 10 or 12 bits) control bits for sample n + 2 (cs = 0, 2 or 4 bits) adc converter sample n + 3 (n = 8, 10 or 12 bits) control bits for sample n + 3 (cs = 0, 2 or 4 bits) lane 0 s[n][15:0] s[n + 1][15:0] s[n + 2][15:0] s[n + 3][15:0] lane 1 lane 2 lane 3 lane 4 lane 5 lane6 lane 7 user defined adc sample n (12 bits) adc sample n + 1 (12 bits) adc sample n + 2 (12 bits) adc sample n + 3 (12 bits) 48 bits @ f s /4 64 bits @ f s /5 64 bits @ f s /5 adc sample n (12 bits) adc sample n + 1 (12 bits) adc sample n + 2 (12 bits) adc sample n + 3 (12 bits) adc sample n + 4 (12 bits) (4 bits) s[n][11:0], s[n + 1][11:8] (16 bits) s[n + 1][7:0], s[n + 2][11:4] (16 bits) s[n + 2][3:0], s[n + 3][11:0] (16 bits) s[n + 4][11:0], ud[3:0] (16 bits) jesd sample n (16 bits) jesd sample n + 1 (16 bits) jesd sample n + 2 (16 bits) jesd sample n + 3 (16 bits) jesd204b framer + phy (m = 1; l = 8; s = 4; f = 1; n = 16; n' = 16; cf = 0; scr = 0, 1; hd = 1; k = see spec 1 1814-033 rev. 0 | page 33 of 56
ad9625 data sheet rev. 0 | page 34 of 56 figure 48. power su pply recommendation 11814-054 adp1740 ldo adp1740 ldo adp1740 ldo adp1740 ldo adp125 ldo adp125 ldo adp2386 buck regulator 2.1v adp2386 buck regulator 3.6v 1.3v: avdd1 2.5v: avdd2 1.3v: drvdd1 1.3v: dvdd1 2.5v: drvdd2 2.5v: dvddio 2.5v: spi_dvddio 2.5v: dvdd2 12v inpu t
data sheet ad9625 serial port interfac e (spi) the ad9625 spi allows the user to configure the converter for specific functions or operations through a structured register space provided inside the adc. the spi gives the user added flexibility and customization, depending on the application. addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be furth er divided into fields. these fields are documented in the memory map section. configuration using the spi three pins define the spi of this adc: the sclk pin, the sdio pin, and the csb pin (see table 18 ). the sclk (serial clock) pin is used to synchronize the read and wri te data presented from/to the adc. the sdio (serial data input/output) pin is a dual - purpose pin that allows data to be sent and read from the internal adc memory map registers. the csb (chip select bar) pin is an active low control that enables or disable s the read and write cycles. table 18 . serial port interface pins pin function sclk serial clock. the serial shift clock input, which is used to synchronize serial interface , reads and writes. sdio serial data input/output. a dual - purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. csb chip select bar. an active low control that gates the read and write cycles. the falling edge of csb , in conjunction with the rising edge of sclk, determines the start of the framing. an example of the serial timing and its definitions can be found in table 5 and figure 3 . other modes involving th e csb pin are available. the csb pin can be held low indefinitely, which permanently enables the device; this is called streaming. the csb pin can stall high between bytes to allow for additional external timing. whe n csb is tied high, spi functions are placed in a high impedance mode . this mode turns on any spi pin secondary functions. all data is composed of 8 - bit words. the first bit of each individual byte of serial data indicates whether a read or write command is issued. this allows the sdio pin to change direction from an input to an output. in addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on - chip memory. if the instructi on is a readback operation, performing a readback causes the sdio pin to change direction from an input to an output at the appropriate point in the serial frame. data can be sent in msb first mode or in lsb first mode. msb first is the default on power - up and can be changed via the spi port configuration register. hardware interface the pins described in table 18 comprise the physical interface between the user prog ramming device and the serial port of the ad9625 . the sclk pin and the csb pin function as inputs when using the spi interface. the sdio pin is bidirectional, functioning as an input during write phases and as an output during readback. the spi interface i s flexible enough to be controlled by either fpgas or microcontrollers. one method for spi configuration is described in detail in the an - 812 application note , microcontroller - based serial port in terface (spi) boot circuit . d o not activate t he spi port during periods when the full dynamic performance of the converter is required. because the sclk signal, the csb signal , and the sdio signal are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on - board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the ad 9625 to prevent these signals from transitioning at the converter inputs during critical sampling periods. rev. 0 | page 35 of 56
ad9625 data sheet memory map reading the memory m ap register each row in the memory map register contains eight bit locations. the memory map is roughly divided into three sections: the chip configuration registers (address 0x000 to address 0x002); the transfer register (address 0x0ff); and the adc functions registers, including setup, control, and te st (address 0x008 to address 0x13a). the memory map register tables pro vid s the default hexadecimal value for each hexadecimal address that is listed . the column with the heading , bit 7 (msb) , is the start of the default hexadecimal value given. for exampl e, address 0x14, the output mode register, has a hexadecimal default value of 0x01. this means that bit 0 = 1, and the remaining bits are 0s. this setting is the default output format value, which is twos complement. for more information on this function a nd others, see the an - 877 application note , interfacing to high speed adcs via spi . open a nd reserved locations all address and bit locations are not currently supported for this device. unused bits of a valid address location should be written with 0s. writing to these locations is required only when a portion of an address location is open. if the entire address location is open, this address location should not be written. default values after the ad9625 is reset, critical registers are loaded with default values. the default values for the registers are given in the memory map register table s. logic levels an explanation of logic leve l terminology follows: ? bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. ? clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit. transfer register map address 0x 0 08 to address 0x 0 20 are shadowed. writes to these addresses do not affect device operation until a transfer command is issued by writing 0x01 to address 0x 0 f f, thereby setting the transfer bit. this allows these registers to update internally and simultaneously when the tran sfer bit is set. the internal update occurs when the transfer bit is set, and then the bit auto matically clears. memory map register s a ddress and bit locations that are not included in table 19 through table 106 are not currently supported for this device. table 19 . spi configuration register, address 0x000 (default = 0x00) bit no. access bit description 7 unused . 6 rw spi least significant bit (lsb) first . 1: lsb shifted first for all spi o perations. for multi byte spi operations, the addressing increments automatically. 0: m ost significant bit (msb) shifted first for all spi operations. for multi byte spi operations, the addressing decrements automatically. 5 rw self clearing soft reset . 1: r eset the spi r egisters (self clearing) . 0: d o nothing . 4 r 13 - bit a ddressing enabled . 3 r 13 - bit a ddressing enabled . 2 rw self clearing soft reset . 1: r eset the spi r egisters(self clearing) . 0: d o nothing. 1 rw spi lsb first. 1: lsb shifted first for all spi operations. for multi - byte spi operations, the addressing increments automatically. 0: msb shifted first for all spi operations. for multi - byte spi operations, the addressing decrements automatically. 0 unused unused . table 20 . chip id register, address 0x001 (default = 0x00) bit no. access bit description [7:0] r chip id . rev. 0 | page 36 of 56
data sheet ad9625 table 21 . chip grade register, address 0x002 (default = 0x00) bit no. access bit description [ 7:6 ] unused . [ 5:4 ] r chip id/ speed grade . 3 unused . [ 2:0 ] r chip die revision . 000: first silicon . 001 to 111: r eserved . table 22 . power control mode register, address 0x008 (default = 0x00) bit no. access bit description 7 unused . 6 unused . 5 unused . [ 4:2 ] unused . [ 1:0 ] rw chip power modes . 00: normal mode (power - up) . 01: reserved . 10: standby mode; digital datapath clocks disabled, jesd204b interface enabled, outputs enabled. 11: digital data path reset mode; digital data path clocks enabled, digital data path held in reset, jesd204b interface held in reset, outputs enabled. table 23. pll status register, address 0x00a (default = 0x00) bit no. access bit description 7 r o pll locked status bit. 0: pll is unlocked. 1: pll is locked. [6:0] unused. table 24. adc test control register , address 0x00d (default = 0x00) bit no. access bit description 7 rw adc data path user test mode control . note: these bits are only used when r eg ister 0x00d , bits [3:0] is in user input mode ( r eg ister 0x00d [3:0] = 1000); o therwise, they are ignored. 0 = continuous/repeat pattern mode . place each user pattern (1, 2, 3, 4) on the output for one clock cycle and then repeat. (output user pattern : 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4, ) 1 = s ingle pattern mode . place each user pattern (1, 2, 3, 4) on the output for one clock cy cle and then output all zeros. (output user pattern : 1, 2, 3, 4, then output all zeros . ) 6 unused . 5 rw adc long psuedo random number test generator reset . 0: l ong pn e nabled . 1: l ong pn h eld in reset . 4 rw unused . [ 3:0 ] rw adc data output test generation mode. 0000: o ff , normal operation. 0001: m idscale short . 0010: positive full scale . 0011: negative full scale . 0100: alternating checker board . 0101: pn sequence, long . 0110: u nused . 0111: one -/ zero - word toggle . 1000: user test mode . u sed with r eg ister 0x00d[7] and user pattern ( 1, 2, 3, 4 ) registers. 1001 to 1110: u nused . 1111: ramp outpu t. rev. 0 | page 37 of 56
ad9625 data sheet table 25. data path customer offset register , address 0x010 (default = 0x00) bit no. access bit description [ 7:6 ] unused . [ 5:0 ] rw digital data path offse t. two s complement offset adjustment aligned with least converter resolution . 011111: + 31 011110: + 30 000001: 1 000000: 0 111111: ? 1 100001: ? 31 100000: ? 32 table 26. output mode register , address 0x014 (default = 0x00) bit no. access bit description [ 7:5 ] unused . 4 rw chip output disable . bit 4 enables and disables the digital outputs from the adc. 0: enable. 1: disable . 3 unused . 2 rw digital adc sample invert . 0: adc sample data is not inverted . 1: adc sample data is inverted . [ 1:0 ] rw digital adc data format select (dfs) . note: t he use of the muxed sdio pin to control register 0x014[1:0] is not supported on the ad9625 . 00: offset binary . 01: two s complement (default) . 10: r eserved . 11: r eserved . table 27. serializer output adjust , register , address 0x015 ( default = 0x50 ) bit no. access bit description 7 rw serializer output polarity selection . 0: normal, not inverted . 1: output driver polarity inverted . [ 6:5 ] rw s erializer output emphasis amplitude control . 00: 0 mv emphasis differential p -p . 01: 160 mv emphasis differential p -p . 10: 80 mv emphasis differential p -p . 11: 40 mv a mplitude differential p - p . [ 4:0 ] rw reserved . table 28. user test pat tern 1 lsb register, address 0x019 (default = 0x00) bit no. access bit description [7:0] rw user test pattern 1 least significant byte. note: t hese bits are used only when register 0x00d, bits [3:0] is in user input mode ( r eg ister 0x00d [3:0] = 1000), o r when r eg ister 0x061, bits [3:0] is in the scrambler or 10 -b it test modes ( r eg ister 0x061[3:0] = 0100 to 0111). otherwise, the se bits are ignored. table 29. user test pat tern 1 msb register, address 0x01a (default = 0x00) bit no. access bit description [7:0] rw user test p attern 1 most significant byte. note: these bits are used only when r egister 0x00d , bits [3:0] is in user input mode ( r eg ister 0x00d [3:0] = 1000). otherwise, the se bits are ignored. rev. 0 | page 38 of 56
data sheet ad9625 table 30. user test pat tern 2 lsb register , address 0x01b (default = 0x00) bit no. access bit description [7:0] rw user test pa ttern 2 least significant byte. note: t hese bits are used only when r eg ister 0x00d , bits [3:0] is in user input mode ( r eg ister 0x00d[3:0] = 1000). otherwise, the se bits are ignored. table 31. user test pat tern 2 msb register, address 0x01c (default = 0x00) bit no. access bit description [7:0] rw user test pattern 2 most significant byte . note: t hese bits are used only when r eg ister 0x00d, bits [3:0] is in user input mode ( r eg ister 0x00d[3:0] = 1000). otherwise, the se bits are ignored. table 32. user test pattern 3 lsb register, address 0x01d (default = 0x00) bit no. access bit description [7:0] rw user test pattern 3 least significant byte. note: t hese bits are used only when r eg ister 0x00d, bits [3:0] is in user input mode (r eg ister 0x00d [3:0] = 1000). otherwise, the se bits are ignored. table 33. user test pat tern 3 msb re gister, address 0x01e (default = 0x00) bit no. access bit description [7:0] rw user test pattern 3 most significa nt byte. no te: t hese bits are used only when r eg ister 0x00d, bits [3:0] is in user input mode (r eg ister 0x00d [3:0] = 1000). otherwise, the se bits are ignored. table 34. user test pattern 4 lsb register, address 0x01f (default = 0x00) bit no. access bit description [7:0] rw user test pattern 4 least significan t byte . note: t hese bits are used only when r eg ister 0x00d , bits [3:0] is in user input mode (r eg ister 0x00d [3:0] = 1000). otherwise, the se bits are ignored. table 35. user test pat tern 4 msb register , address 0x020 (default = 0x00) bit no. access bit description [7:0] rw user test pattern 4 most significa nt byte. note: t hese bits are used only when r eg ister 0x00d , bits [3:0] is in user input mode (r eg ister 0x00d [3:0] = 1000). otherwise, the se bits are ignored. table 36. s ynthesizer pll control register, address 0x021 (default = 0x00) bit no. access bit description [ 7:5 ] unused . 4 rw 1 = force power - down of vco ldo 3 rw reserved for future use. [2:0] unused . table 37. adc analog input control register, address 0x02c (default = 0x00) bit no. access bit description [ 7:3 ] unused . 2 rw set function on vmon pin. 0: unused . 1: allow customer to apply external reference on vmon pin. [ 1:0 ] unused . table 38. sysref control register, address 0x03a (default = 0x00) bit no. access bit description 7 rw sysref status bit replaces the lsb from the converter. 0: normal mode. 1: sysref status bit replaces the lsb. 6 rw sysref status bit flag reset. to use the flags, register 0x03a, bit 1 must be set to high. 0: normal flag operation. 1: sysref status bit flags held in reset. 5 unused. 4 rw sysref trans i tion selection. 0: sysref is valid on low to high transitions using selected clk edge. 1: sysref is valid on high to low transitions using selected clk edge. rev. 0 | page 39 of 56
ad9625 data sheet bit no. access bit description 3 rw sysref capture edge selection. 0: captured on rising edge of clk input. 1: captured on falling edge of clk input. 2 rw sysref next mode. 0: continuous mode. 1: next sysref mode: uses the next valid edge only of the sysref pin. subsequent edges of the sysref pin are ignored. when the next system reference is found, bit 1 of register 0x03a clears. 1 rw sysref pins enable. 0: sysref disabled. 1: sysref enabled. when register 0x03a, bit 2 = 1, only the next valid edge of the sysref pins is used. subsequent edges of the sysref pin are ignored. 0 unused . table 39 . fast dete ct control register , address 0x045 (default = 0x00) bit no. access bit description [ 7:4 ] unused . 3 rw force the fast detect output pin . 0: n ormal operation of fast detect pin . 1: force a value on the fast detect pin (see bit 2 in this table, table 39). 2 rw the fast detect output pin is set to the value in this bit ( r egister 0x045[2]) when the output is forced. 1 unused . 0 rw enable fast detect on the corrected adc d ata . 0: fine fast detect disabled . 1: fine fast detect enabled . table 40. fast detect upper threshold register , address 0x047 (default = 0x00) bit no. access bit description [7:0] rw these bits are the lsbs of the fast detect upper threshold . these eight lsb s of the p rogrammable 12 - bit upper threshold are compared to the fine adc magnitude . table 41. fast detect upper threshold register , address 0x048 (default = 0x00) bit no. access bit description [ 7:4 ] unused . [ 3:0 ] rw these bits are the msbs of the fast detect upper threshol d. these four msb s of the programmable 12 - bit upper threshold are compared to the fine adc magnitude. table 42. fast detect lower threshold register , address 0x049 (default = 0x00) bit no. access bit description [7:0] rw these bits are the lsbs of the fast detect lower thr eshold. these eight lsb s of t he p rogrammable 12 - bit lower threshold are compared to the fine adc magnitude . table 43. fast detect lowerthreshold register , address 0x04a (default = 0x00) bit no. access bit description [ 7:4 ] unused . [3:0] rw msbs of the fast detect lower threshold. these four msb s of the programmable 12 - bit lower threshold are compared to the fine adc magnitude. table 44. fast detect dwell time counter threshold register, address 0x04b (default = 0x00) bit no. access bit description [7:0] rw these bits are the lsbs of the fast detect dwell time counter target. this is the value for a 16 - bit counter that determines the length of time that the adc data must remain below the lower threshold before the fd pin reset to 0. rev. 0 | page 40 of 56
data sheet ad9625 table 45. fast detect dwell time counter threshold register , address 0x04c (default = 0x00) bit no. access bit description [7:0] rw these bits are the msbs of the fast detect dwell time counter target. this is the value for a 16 - bit counter that determines the length of time that the adc data must remain below the lower threshold before the fd pin reset s to 0. note that the fast detect (fd) pin deasserts after the adc codes stay below the lower target for the number of samples indicated by the value in reg ister 0x04c[7:0] . table 46. jesd204b quick configuration register, address 0x05e (default = 0x00) bit no. access bit description [7:0] rw jesd204b serial quick configuration (self clearing) . t his register is self clearing and does not control anything in the ad9625 directly; i t only ch anges the value of the ot her jesd240b regi sters that control the chip. because this register is self clearing, it always re turn s to 000 after each write. to use the quick configuration feature, write to this register first, then , if there are any changes that need to be made to any of the following settin gs, write to the o ther jesd204b re gisters. 0x00: c onfiguration determined by other registers. because the register is self clearing, it always return s to this value after each write. 0x01: r eserved . 0x02: generic 2 lane config uration r eg ister 0x063 [3:0] = 0x0; r eg ister 0x06e[4:0] = 0x1; register 0x072[4:0] = 0xb; register 0x073[4:0] = 0xf. 0x04: generic 4 lane config uration register 0x063 [3:0] = 0x0; register 0x06e[4:0] = 0x3; register 0x072[4: 0] = 0xb; register 0x073[4:0] = 0xf. 0x06: generic 6 lane config uration register 0x063 [3:0] = 0x0; register 0x06e[4:0] = 0x5; register 0x072[4:0] = 0xb; register 0x073[4:0] = 0xb. 0x08: generic 8 lane config uration register 0x063 [3:0] = 0x0; register 0x06e[4:0] = 0x7; register 0x072[4:0] = 0xb; register 0x073[4:0] = 0xf. 0x18: r eserved . 0x28: r eserved . 0x48: f s 2 mode, eight lanes. register 0x063[3:0] = 0x4; register 0x06e[4:0] = 0x7; register 0x072[4:0] = 0xf; register 0x073[4:0] = 0xf. 0x81: 1 ddc (high bw), one lane. register 0x063[3:0] = 0x8; register 0x06e[4:0] = 0x0; register 0x072[4:0] = 0xf; register 0x073[4:0] = 0xf. 0x82: 1 ddc (high bw), two lanes. register 0x063[3:0] = 0x8; register 0x06e[4:0] = 0x1; register 0x072[4:0] = 0xf; register 0x073[4:0] = 0xf. 0x91: 1 ddc (low bw), one lane. register 0x063[3:0] = 0x9; register 0x06e[4:0] = 0x0; register 0x072[4:0] = 0xf; register 0x073[4:0] = 0xf. 0xc1: 2 ddcs (high bw), one lane. register 0x063[3:0] = 0xc; register 0x06e[4:0] = 0x0; register 0x072[4:0] = 0xf; register 0x073[4:0] = 0xf. 0xc2: 2 ddcs (high bw), two lanes. register 0x063[3:0] = 0xc; register 0x06e[4:0] = 0x1; register 0x072[4:0] = 0xf; register 0x073[4:0] = 0xf. 0xc4: 2 ddcs (high bw), four lanes. register 0x063[3:0] = 0xc; register 0x06e[4:0] = 0x3; register 0x072[4:0] = 0xf; register 0x073[4:0] = 0xf. 0xd1: 2 ddcs (low bw), one lane. register 0x063[3:0] = 0xd; register 0x06e[4:0] = 0x0; register 0x072[4:0] = 0xf; register 0x073[4:0] = 0xf. 0xd2: 2 ddcs (low bw), two lanes. register 0x063[3:0] = 0xd; register 0x06e[4:0] = 0x1; register 0x072[4:0] = 0xf; register 0x073[4:0] = 0xf. 0xe1: 2 ddcs (mixed bw), one lane. register 0x063[3:0] = 0xe; register 0x06e[4:0] = 0x0; register 0x072[4:0] = 0xf; register 0x073[4:0] = 0xf. 0xe2: 2 ddcs (mixed bw), two lanes. register 0x063[3:0] = 0xe; register 0x06e[4:0] = 0x1; register 0x072[4:0] = 0xf; register 0x073[4:0] = 0xf. 0xe4: 2 ddcs (mixed bw), four lanes. register 0x063[3:0] = 0xe; register 0x06e[4:0] = 0x3; register 0x072[4:0] = 0xf; register 0x073[4:0] = 0xf. all other values have no effect. rev. 0 | page 41 of 56
ad9625 data sheet table 47. jesd204b link control register 1 , address 0x05f (default = 0x00) bit no. access bit description 7 unused . 6 rw jesd204b serial tail bit , pn , e nable . note: t he following equation can be used to determine the number of pn bits sent per sample = n ' ? n C cs (the number of control bits per sample) . 0: serial tail b it , pn , disabled. unused extra tail bits ar e padded with zeros. 1: serial tail b it , pn , enabled. unused extra tail bits ar e padded with a pseudo r andom n umber s equence from a 31 - bit lfsr (see jesd204b 5.1.4). 5 rw jesd204b serial test sample enable . 0: jesd204b test samples disabled . 1: jesd204b test samples enabled . the t ransport layer test sample sequence (as specified in jesd204b s ection 5.1.6.2) is sent on all link lanes. 4 rw jesd204b serial lane synchronization enabl e. note that the frame character inserti on must be enabled (register 0x05f[1] = 0) to enable lane synchronization. 0: lane synchronization disabled. both sides do not perform lane sync hronization; frame alignment character inse rtion always uses /k28.7/ control characters (see jesd204b 5.3.3.4) . 1: lane synchronization enabled. both sides perform lane sync ; frame alignment character inse rtion uses either /k28.3/ or /k28.7/ control characters (see jesd204b 5.3.3.4) . [ 3:2 ] rw jesd204b s erial initial lane alignment sequence mode . 00: initial l ane alignment sequence disabled (jesd204b 5.3.3.5) . 01: initial lane alignment sequence enabled (jesd204b 5.3.3.5) . 10: r eserved . 11: i nitial lane alignment sequence always on test mode ; the jes d204b data link layer test mode ( where re peated lane alignment sequence, as specified in jesd204b section 5.3.3.9.2) is sent on all lanes. 1 rw jesd204b serial frame alignment character insertion (faci) d isable . 0: frame alignment character insertion enabled (jesd204b 5.3.3.4) . 1: frame alignment character insertion disabled . note that this is f or debug only (jesd204b 5.3.3.4) . 0 rw jesd204b serial transmit link power - down (active high) . note that t he jesd204b transmitter link must be powered down while changing any of the link configuration bits. 0: jesd204b serial transmit link enabled. transmission of the /k28.5/ characters for code group synchronization is controlled by the syncinb pins . 1: jesd204b serial transmit link powered down (held in reset and clock gated). table 48. j esd204b link control register 2, address 0x060 (default = 0x00) bit no. access bit description [ 7:6 ] rw jesd204b serial sync mode. 00: normal mode. 01: reserved . 10: syncinb active mode. syncinb pins are active: force code group synchronization. 11: syncinb pins disabled. 5 rw jesd204b serial sync pin invert. 0: syncinb pins not inverted. 1: syncinb pins inverted. [ 4:3 ] unused . 2 rw jesd204b serial 8 -b it /10 -b it b ypass (test mode only) . 0: 8 -b it /10 -b it enabled . 1: 8 -b it /10 -b it bypassed ( m ost significant two bits are 0) . 1 rw jesd204b 10 -b it serial transmit bit invert . note that in the event that the cml signals are reverse d in a system board layout , this bit effectively invert s the differential outputs from the phy . 0: n ormal . 1: invert the a , b , c , d , e , f , g , h , i, j bits. 0 rw jesd204b 10- bit serial transmit bit mirror. 0: 10 - bit serial bits are not mirrored. transmit bit order is alphabetical: a, b, c, d, e, f, g, h, i , j. 1: 10 - bit serial bits are mirrored. transmit bit order is alphabetically reversed: j, i , h, g, f, e, d, c, b, a. rev. 0 | page 42 of 56
data sheet ad9625 table 49. jesd204b link control register 3 , address 0x061 ( default = 0x00 ) bit no. access bit description 7 rw jesd204b checksum disable . 0: checksum enabled in the link configuration parameter. normal operation. 1: checksum disabled in the l ink configur ation parameter (set to zero). for testing purposes only. 6 rw jesd204b checksum mode . 0: checksum is the sum of all 8 - bit registers in the link configuration field s. 1: checksum is the sum of all individual link configuration fields (lsb aligned). [ 5:4 ] rw jesd204b serial test generation input selection . 00: 16 - bit test generation data injected at the sample input to the link . 01: 10 - bit test generation data injected at the output of the 8 - b it /10 - b it encoder (at the input to phy) . 10: 8 - bit test generation data injected at the i nput of the s crambler . 11: reserved . [ 3:0 ] rw jesd204b serial test generation mode . 0000: normal operation (test mode disabled) . 0001: alternating checker board . 0010: 1/0 word toggle . 0011: pn sequence ( long ). 0100: unused . 0101: continuous/repeat user test mode . the most significant bits from the user pattern (1, 2, 3, 4) are placed on the output for one clock cycle and then repeat ed (the output user pattern is 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4, ) . 0110: single user test mode . the most significant bits from the user pattern (1, 2, 3, 4) are placed on the output for one clock cy cle and then output all zeros (the o utput user pattern is 1, 2, 3, 4, and then output s all zeros) . 0111: ramp output . 1000: modified rpat test sequence ( 10- bit value ). 1001: u nused . 1010: jspat test sequence ( 10- bit value ) . 1011: jtspat test sequence ( 10- bit value ) . 1100 to 1111: unused . table 50. jesd204b link cont rol register 4 , address 0x062 (default 0x00) bit no. access bit description [7:0] rw initial lane alignment sequence repeat count. bits[7:0] specify the number of times the initial lane alignment sequence repeats. for adcs, the jesd204b specification states that the initial lane alignment sequence always spans four multiframes (jesd204b 5.3.3.5). because register 0x070, bits[4:0] determine the number of frames per multiframe, the total number of frames transmitted during the initial lane alignment sequence = 4 (register 0x070[4:0] + 1) (register 0x062[7:0] + 1). table 51. jesd204b link control register 5, address 0x063 ( default = 0x00 ) bit no. access bit description 7 unused . [ 6:4 ] unused . [ 3:0 ] rw jesd204b application layer mo de. ddc bandwidth modes are as follows: high bandwidth, decimate by 8 (effective output bandwidth = f s /10) and low bandwidth, decimate by 16 (effective output bandwidth = f s /20). 0000: generic (no application layer used). 0001: unused. 0010: unused. 0011: unused. 0100: f s x mode (where x is an integer). 0101 to 0111: unused. 1000: single ddc mode (high bandwidth mode (only ddc 0 used) . 1001: single ddc mode (low bandwidth mode (only ddc 0 used) . 1010 to 1011: unused. 1100: dual ddc mode , high bandwidth mode (both ddc 0 and ddc 1 used ). 1101: dual ddc mode , low bandwidth mode (both ddc 0 and ddc 1 used) . 1110: dual ddc mode , mixed bandwidth mode ( ddc 0 high bandwidth mode, ddc 1 low bandwidth mode, samples repeated) . 1111: unused . rev. 0 | page 43 of 56
ad9625 data sheet table 52. jesd204b configuration register , address 0x064 ( default = 0x00 ) bit no. access bit description [7:0] rw jesd204b serial device identification (did) number. table 53. jesd204b configuration register , address 0x065 ( default = 0x00 ) bit no. access bit description [ 7:4 ] unused . [ 3:0 ] rw jesd204b serial b ank identification (bid) number (extension to did) . table 54. jesd204b configuration register , address 0x066 ( default = 0x00 ) bit no. access bit description [7:5] unused. [4:0] rw jesd204b serial lane identification (lid) number for lane 0. table 55. jesd204b configuration register, address 0x067 (default = 0x 01 ) bit no. access bit description [7:5] unused. [4:0] rw jesd204b serial lane identification (lid) number for lane 1. table 56. jesd204b configuration register, address 0x068 (default = 0x 02 ) bit no. access bit description [7:5] unused. [4:0] rw jesd204b serial lane identification (lid) number for lane 2. table 57. jesd204b configuration register, address 0x069 (default = 0x 03 ) bit no. access bit description [7:5] unused. [4:0] rw jesd204b serial lane identification (lid) number for lane 3. table 58. jesd204b configuration register, address 0x06a (default = 0x 04 ) bit no. access bit description [7:5] unused. [4:0] rw jesd204b serial lane identification (lid) number for lane 4. table 59. jesd204b configuration register, address 0x06b (default = 0x 05 ) bit no. access bit description [7:5] unused. [4:0] rw jesd204b serial lane identification (lid) number for lane 5. table 60. jesd204b configuration register, address 0x06c (default = 0x 06 ) bit no. access bit description [7:5] unused. [4:0] rw jesd204b serial lane identification (lid) number for lane 6. table 61. jesd204b configuration register, address 0x06d (default = 0x 07 ) bit no. access bit description [7:5] unused. [4:0] rw jesd204b serial lane identification (lid) number for lane 7. table 62. jesd204b configuration register, address 0x06e (default = 0x 87 ) bit no. access bit description 7 rw jesd204b serial scrambler mode. 0: jesd204b scrambler disabled (scr = 0). 1: jesd204b scrambler enabled (scr = 1). [6:5] unused. rev. 0 | page 44 of 56
data sheet ad9625 bit no. access bit description [4:0] rw jesd204b serial lane control (l = register 0x06e[4:0] + 1) . 0: one lane per link (l = 1). 1:two lanes per link (l = 2). 2: unused. 3: four lanes per link (l = 4). 4: unused. 5: six lanes per link (l = 6). 6: unused. 7: eight lanes per link (l = 8). 8 to 31: unused. table 63. jesd204b configuration register, address 0x06f (default = 0x00) bit no. access bit description [7:0] ro jesd204b number of octets per frame (f = register 0x06f[7:0] + 1) . t hese bits are calculated using the following equation: f ( n )( l ) the folloing are v alid values of f m s n l f m s n l f m s n l f m s n l f m s n l f (default) table 64. jesd204b configuration register, address 0x0 70 ( default = 0x00 ) bit no. access bit description [ 7:5 ] unused . [ 4:0 ] rw jesd204b n umber of frames per multiframe (k = register 0x070[4:0] + 1). only those values that are divisible by four can be used. table 65. jesd204b configuration register, address 0x0 71 ( default = 0x00 ) bit no. access bit description [7:0] ro jesd204b n umbe r of converters per link/device. 0: l ink connected to one adc ( m = 1) . 1 to 255: u nused . table 66. jesd204b configuration register, address 0x0 72 ( defau lt = 0x 0b ) bit no. access bit description [7:6] rw jesd204b number of control bits per sample (cs , based on the jesd204b specification ) . 00: no control bits sent per sample (cs = 0). 01: one control bit sent per sample, overrange bit enabled (cs = 1). 10: two control bits sent per sample, overrange + timestamp sysref bit (cs = 2). 11: reserved. 5 unused. [4:0] rw jesd204b converter resolution (n = register 0x072[4:0] + 1). 0x0 0 to 0x 0 6: reserved. 0x07 to 0x09: reserved. 0x0a: reserved. 0x0b: n = 12 - bit adc converter resolution . 0x0c to 0x0e: r eserved . 0x0f: n = 16- bit adc converter resolution . 0x10 to 0x1f: r eserved . rev. 0 | page 45 of 56
ad9625 data sheet table 67. jesd204b configuration register, address 0x0 73 (default = 0x 2f ) bit no. access bit description [ 7:5 ] rw jesd204b device subclass version . 0x0: subclass 0 . 0x1: subclass 1 (default) . 0x2: subclass 2 (not supported) . 0x3: u ndefined . [ 4:0 ] rw jesd204b t otal number of bits per sample (n' = register 0x073 [4:0] + 1) . 0x0 to 0xa: u nused . 0xb: n' = 12 (l must be equal to 6) . 0xc to 0xe: u nused . 0xf: n'=16 (l must be equal to 1, 2, 4, or 8) . table 68. jesd204b configuration register, addr ess 0x074 (default = 0x 23 ) bit no. access bit description [7:5] rw jesd204b version. 0x0: jesd204a. syncinb pins input are internally gated by the frame clock. syncinb must be low for at least two frame clock cycles to be interpreted as a synchronization request. 0x1: jesd204b. syncinb pins input are internally gated by the local multiframe clock. syncinb must be low for at least four frame clock cycles to be interpreted as a synchronization request. 0x2 to 0x7: undefined. [ 4:0 ] ro jesd204b samples per converter frame cycle (s = register 0x074[4:0] + 1). these are r ead - only bits. for the ad9625, s must be equal to 4 (register 0x074[4:0] = 3). table 69. jesd204b configuration register, address 0x075 (default = 0x 80 ) bit no. access bit description 7 ro jesd204b high density (hd) format . this is a r ead - only bit. 0: hd f ormat d isabled . 1: hd f ormat e nabled . high density mode is automatically enabled based on the values of n' and l. t he values of hd for the ad9625 are as follows : n' = 16, l = 1 , hd = 0 . n' = 16, l = 2 , hd = 0 . n' = 16, l = 4 , hd = 0 . n' = 12, l = 6 , hd = 1 . n' = 16, l = 8 , hd = 1 (default) . [ 6:5 ] unused . [ 4:0 ] ro jesd204b number of control words per frame clock cycle per link (cf) . these are read - only bits. for the ad9625, cf must equal 0 (register 0x075[4:0] = 0). table 70. jesd204b configuration register, address 0x076 (default = 0x00) bit no. access bit description [7:0] rw jesd204b serial reserved field 1 . table 71. jesd204b configuration register, address 0x077 (default = 0x00) bit no. access bit description [7:0] rw jesd204b serial reserved field 2 . table 72. jesd204b configuration register, address 0x078 (default = 0x00) bit no. access bit description [7:0] ro jesd204b serial checksum value for lane 0. this value is a utomatic ally calculated the value = ( the s um of all link confi guration parameters for lane 0 ) m od ulus 256 . checksum is enabled/disabled using register 0x061 , bit 7. table 73. jesd204b configuration register, address 0x079 (default = 0x00) bit no. access bit description [7:0] ro jesd204b serial checksum value for lane 1. this value is automatically calculated. the value = ( the sum of all link configuration parameters for lane 1 ) m odulus 256. checksum is enabled/disabled using register 0x061, bit 7. rev. 0 | page 46 of 56
data sheet ad9625 table 74. jesd204b configuration register, address 0x07a (default = 0x00) bit no. access bit description [7:0] ro jesd204b serial checksum value for lane 2. this value is automatically calculated . the value = ( the sum of all link configuration parameters for lane 2 ) m odulus 256. checksum is enabled/disabled using register 0x061, bit 7. table 75. jesd204b configuration register, address 0x07b (default = 0x00) bit no. access bit description [7:0] ro jesd204b serial checksum value for lane 3. this value is automatically calculated. the value = ( the sum of all link configuration parameters for lane 3 ) m odulus 256 . checksum is enabled/disabled using register 0x061, bit 7. table 76. jesd204b configuration register, address 0x07c (default = 0x00) bit no. access bit description [7:0] ro jesd204b serial checksum value for lane 4. this value is automatically calculated . the value = ( the sum of all link configuration parameters for lane 4 ) m odulus 256. checksum is enabled/disabled using register 0x061, bit 7. table 77. jesd204b configuration register, address 0x07d (default = 0x00) bit no. access bit description [7:0] ro jesd204b serial checksum value for lane 5. this value is automatically calculated. the value = ( the sum of all link configuration parameters for lane 5 ) m odulus 256. checksum is enabled/disabled using register 0x061, bit 7. table 78. jesd204b configuration register, address 0x07e (default = 0x00) bit no. access bit description [7:0] ro jesd204b serial checksum value for lane 6. this value is automatically calculated. the value = ( the sum of all link configuration parameters for lane 6 ) m odulus 256 . checksum is enabled/disabled using register 0x061, bit 7. table 79 . jesd204b configuration register, address 0x07f (default = 0x00) bit no. access bit description [7:0] ro jesd204b serial checksum value for lane 6. this value is automatically calculated . the value = ( the sum of all link configuration parameters for lane 6 ) m odulus 256. checksum is enabled/disabled using register 0x061, bit 7. table 80 . jesd204b lane power - down registe r, address 0x080 (default = 0x00) bit no. access bit description 7 rw physical lane h power - down. 0: lane h enabled. 1: lane h powered down . 6 rw physical lane g power - down. 0: lane g enabled. 1: lane g powered down. 5 rw physical lane f power - down. 0: lane f enabled. 1: lane f powered down. 4 rw physical lane e power - down. 0: lane e enabled. 1: lane e powered down. 3 rw physical lane d power - down . 0: lane d enabled . 1: lane d powered down . 2 rw physical lane c power - down. 0: lane c enabled. 1: lane c powered down. 1 rw physical lane b power - down. 0: lane b enabled. 1: lane b powered down. 0 rw physical lane a power - down. 0: lane a enabled. 1: lane a powered down. rev. 0 | page 47 of 56
ad9625 data sheet table 81. jesd204b lane control register 1, address 0x082 (default = 0x 10 ) bit no. access bit description 7 unused . [6:4] rw physical lane b assignment. 000: logical lane 0. 001: logical lane 1 (default). 010: logical lane 2. 011: logical lane 3. 100: logical lane 4. 101: logical lane 5. 110: logical lane 6. 111: logical lane 7. 3 unused . [2:0] rw physical lane a a ssignment . 000: logical lane 0 (default). 001: logical lane 1 . 010: logical lane 2 . 011: logical lane 3 . 100: logical lane 4 . 101: logical lane 5 . 110: logical lane 6 . 111: logical lane 7 . table 82. jesd204b lane control register 2, address 0x083 (defaul t = 0x 42 ) bit no. access bit description 7 unused . [ 6:4 ] rw physical lane d a ssignment . 000: logical lane 0 . 001: logical lane 1 . 010: logical lane 2 . 011: logical lane 3 (default). 100: logical lane 4 . 101: logical lane 5 . 110: logical lane 6 . 111: logical lane 7 . 3 unused . [ 2:0 ] rw physical lane c a ssignment . 000: logical lane 0 . 001: logical lane 1 . 010: logical lane 2 (default). 011: logical lane 3 . 100: logical lane 4 . 101: logical lane 5 . 110: logical lane 6 . 111: logical lane 7 . rev. 0 | page 48 of 56
data sheet ad9625 table 83. jesd204b lane control register 3, address 0x084 (d efault = 0x 54 ) bit no. access bit description 7 unused . [ 6:4 ] rw physical lane f a ssignment . 000: logical lane 0 . 001: logical lane 1 . 010: logical lane 2 . 011: logical lane 3 . 100: logical lane 4 . 101: logical lane 5 (default). 110: logical lane 6 . 111: logical lane 7 . 3 unused . [ 2:0 ] rw physical lane e a ssignment . 000: logical lane 0 . 001: logical lane 1 . 010: logical lane 2 . 011: logical lane 3 . 100: logical lane 4 (default). 101: logical lane 5 . 110: logical lane 6 . 111: logical lane 7 . table 84. jesd204b lane control register 4, address 0x085 (default = 0x 76 ) bit no. access bit description 7 unused . [ 6:4 ] rw physical lane h a ssignment . 000: logical lane 0 . 001: logical lane 1 . 010: logical lane 2 . 011: logical lane 3 . 100: logical lane 4 . 101: logical lane 5 . 110: logical lane 6 . 111: logical lane 7 (default) . 3 unused . [ 2:0 ] rw physical lane g a ssignment . 000: logical lane 0 . 001: logical lane 1 . 010: logical lane 2 . 011: logical lane 3 . 100: logical lane 4 . 101: logical lane 5 . 110: logical lane 6 (default). 111: logical lane 7 . table 85. unused, address 0x088 (default = 0x00) bit no. access bit description [7:0] rw unused . table 86. unused, address 0x089 (default = 0x00) bit no. access bit description [7:0] rw unused . rev. 0 | page 49 of 56
ad9625 data sheet table 87. unused control register, address 0x08a (default = 0x20) bit no. access bit description [ 7:6 ] unused . [5:4] rw unused; bits [5:4] must be set to 10. [ 3:2 ] unused . [1:0] rw unused; bits [1:0] must be set to 00. table 88. jesd204b local multi f rame clock offset control register , address 0x08b (default = 0x00) bit no. access bit description [ 7:5 ] unused . [ 4:0 ] rw local multiframe clock (lmfc) phase offset value . these bits provide the r eset value for lmfc p hase counter when sysref pins are asserted; this is u sed for deterministic delay applications. table 89. jesd204b local frame clock offset control register, address 0x08c (default = 0x00) bit no. access bit de scription [7:0] rw local frame clock phase offset value . reset value for frame clock phas e counter when sysref pins are asserted. for the ad9625 , only values from 0 to 7 are valid. this is u sed for deterministic delay applications. table 90. customer spare register, address 0x0f8 (default = 0x00) bit no. access bit description [ 7:1 ] rw spare customer register . 0 rw register control to set the ratio between adc sampling clock and divclk . 0 = divide by 4 . 1 = n ot used . table 91. customer spare register , address 0x0f 9 (default = 0x00) bit no. access bit description [7:0] rw spare customer registe r. table 92. customer spare register , address 0x0f f (default = 0x00) bit no. access bit description [ 7:1 ] unused . 0 rw register map master/slave transfer bit . self - clearing bit used to synchronize the transfer of data from the master to the slave registers. 0: n o effect . 1: t ransfer s data from the master registers , written by the register maps , to the slave registers. table 93. interrupt request (irq) status register , address 0x100 (default = 0x00) bit no. access bit description 7 ro interrupt request pll lock error. 1: the pll is unlocked. 6 unused . 5 ro unused . 4 ro unused . 3 ro interrupt request sysref hold error. 1: a hold error has occurred with th e last sysref signal received. to clear this error, set and clear bit 6 in r egister 0x03a . 2 ro interrupt request sysref setup error. 1: a setup error has occurred with the last sysref signal received. to clear this error, set and clear bit 6 in r egister 0x03a. 1 unused . 0 ro interrupt request clock error . rev. 0 | page 50 of 56
data sheet ad9625 table 94. interrupt request (irq) mask control r egister, address 0x101 (default = 0xbf ) bit no. access bit description 7 rw interrupt request pll lock error masked. 1: pll unlocked events are masked. 6 unused . 5 rw must be set to 1. 4 rw must be set to 1. 3 rw interrupt request sysref hold error. 1: a hold error has occurred with the last sysref signal received. to clear this error, set and clear bit 6 in r egister 0x03a. 2 rw interrupt r equest sysref setup error . 1: a setup error has occurred with the last sysref signal received. to clear this error, set and clear bit 6 in register 0x03a. 1 unused . 0 rw interrupt request clock error mask . 1: clock error has occurred and the validity of the output data cannot be guaranteed. the only way to recover from this error is to reset the device. table 95. digital control register, address 0x105 (default = 0x00) bit no. access bit description [ 7:5 ] unused . 4 rw must be set to 0. 3 rw must be set to 0 . 2 rw must be set to 0 . 1 rw must be set to 0 . 0 rw must be set to 0 . table 96. digital calibration threshold control register, address 0x10a (default = 0x10) bit no. access bit description [ 5:7 ] unused . 4 rw enable data set threshold logic for background gain . [0:3] unused . table 97. digital calibration data set threshold register, address 0x10d ( default = 0x3d) bit no. access bit description [7:0] rw data set threshold for background gain calibration . table 98. digital calibration data set threshold register , address 0x10e (default = 0x14) bit no. access bit description [7:0] rw data set threshold for background gain calibration . table 99. calibration register, address 0x12a (default = 0x01) bit no. access bit description [7:0] rw the ad9625 requires a calibration cycle at startup and once every 24 hour period. to perform this calibration at startup, the default value in register 0x12a[7:0] must be overwritten and set to 0x03 at adc startup to initiate the calibration. when the calibration is initiated, the adc needs to remain in this mode for at least 500 clock cycles. during calibration, the output data of the adc is invalid. when the calibration is complete, a successive write of register 0x12a[7:0] to 0x01 terminates the calibration and va lid adc data resumes. to maintain adc performance, repeat this calibration cycle once in every 24 hour period. table 100 . divclk output control register, address 0x120 (default = 0x11) bit no. access bit description [ 7:5 ] unused . 4 rw divclk output disable. 0: divclk output is disabled. 1: divclk output is enabled. rev. 0 | page 51 of 56
ad9625 data sheet bit no. access bit description 3 rw divclk output termination selection. 0: divclk output uses an external 100 resistive termination. 1: divclk output uses no external resistive termination. 2 unused . [1:0] rw control the differential swing for the divclk output. 00 = 100 mv p - p differential. 01 = 200 mv p - p differential. 10 = 300 mv p - p differential. 11 = 400 mv p - p differential. table 101 . ddc 0 gain control register, address 0x130 (default = 0x00) bit no. access bit description [ 7:6 ] unused . [ 5:4 ] rw ddc 0 p olyphase ( d ecima te by 2) gain in units of 6 db. 00: 0 db gain . 01: 6 db g ain . 10: 12 db g ain . 11: 18 db g ain . [ 3:2 ] unused . [ 1:0 ] rw ddc 0 p olyphase ( d ecimate by 8) g ain in units of 6 db. 00: 0 db gain . 01: 6 db gain . 10: 12 db gain . 11: 18 db gain . table 102 . ddc 0 phase increment least significant bits register, address 0x131 (default = 0x00) bit no. access bit description [7:0] rw ddc 0 nco phase increment value. phase inc rement for the nco within ddc 0. the output frequency = ( decimal(register 0x132[1:0]; register 0x13 1 [7:0]) f s )/ 1024 . table 103 . ddc 0 phase increment most significant bits register, address 0x132 (default = 0x00) bit no. access bit description [ 7:2 ] unused . [ 1:0 ] rw ddc 0 nco phase increment v alue. phase increment for the nco within ddc 0. table 104 . ddc 1 gain control register, address 0x138 (default = 0x00) bit no. access bit description [ 7:6 ] unused . [ 5:4 ] rw ddc 1 p olyphase ( d ecima te by 2) gain in units of 6 db. 00: 0 db gain. 01: 6 db gain. 10: 12 db gain. 11: 18 db gain. [3:2] unused. [1:0] rw ddc 1 polyphase (decimate by 8) gain in units of 6 db. 00: 0 db gain. 01: 6 db gain 10: 12 db gain. 11: 18 db gain. table 105 . ddc 1 phase increment least significant bits register, address 0x1 39 (default = 0x00) bit no. access bit description [7:0] rw ddc 1 nco phase increment val ue. phase increment for the nco within ddc 1. the output frequency = ( decimal(register 0x13a[1:0]; register 0x139[7:0]) f s )/ 1024 . rev. 0 | page 52 of 56
data sheet ad9625 table 106 . ddc 1 phase increment most significant bits register, address 0x13a (default = 0x00) bit no. access bit description [ 7:2 ] unused . [ 1:0 ] rw ddc 1 nco phase increment val ue. rev. 0 | page 53 of 56
ad9625 data sheet outline dimensions figure 49 . 196 - ball ball grid array, thermally enhanced [bga_ed] (bp - 196 - 2) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad9625bbpz - 2.0 ? 40c to +85c 196 - ball ball grid array, thermally enhanced [bga_ed] bp -196 -2 ad9625bbpzrl - 2.0 ? 40c to +85c 196 - ball ball grid array, thermally enhanced [bga_ed] , 13 tape and reel bp - 196 - 2 ad9625 - 2.0ebz evaluation board with ad9625 1 z = rohs compliant part. compliant to jedec standards mo-275-ggaa-1. 07-20-2012- a 0.80 0.80 ref 0.51 ref 0.75 ref a b c d e f g 9 10 11 12 13 14 8 7 5 6 4 2 3 1 bottom view 10.40 sq h j k l m n p detail a top view detail a coplanarity 0.12 0.50 0.45 0.40 ball diameter seating plane 12.10 12.00 sq 11.90 a1 ball pad corner a1 ball pad corner 1.70 1.59 1.50 11.20 sq 8.20 sq 1.33 1.26 1.19 0.38 0.33 0.28 rev. 0 | page 54 of 56
data sheet ad9625 notes rev. 0 | page 55 of 56
ad9625 data sheet rev. 0 | page 56 of 56 notes ?2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d11814-0-5/14(0) www.analog.com/ad9625

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